karan kumar
New Delhi
Summary
Professional application engineer with deep technical expertise in software development and systems integration. Proven ability to drive results through effective team collaboration and adaptive problem-solving. Known for reliability, flexibility, and strong focus on achieving project goals.
Overview
6
6
years of professional experience
2
2
years of post-secondary education
Work History
Senior Application Engineer
Cadence Design Systems
02.2022 - Current
- Leveraged Cadence tools (ADE Explorer, Assembler, Spectre, and Liberate portfolio) to streamline IC design processes, ensuring efficient and high-quality design outcomes.
- Characterized standard cell libraries for 28nm and below processes, delivering accurate timing, power, and noise models to meet stringent design requirements.
- Developed and maintained TCL and Shell scripts to automate repetitive characterization tasks, reducing manual effort and enhancing process efficiency.
- Collaborated with cross-functional teams to debug complex design issues, providing timely solutions that improved product performance and customer satisfaction.
- Authored comprehensive technical documentation to support application usage and best practices, enabling effective onboarding and tool adoption for design teams.
- Analyzed customer feedback to identify and implement application enhancements, driving continuous improvement in functionality and user experience.
- Conducted rigorous testing and validation of design applications, ensuring adherence to high-quality standards and reliable performance in production environments.
- Proactively identified and implemented process refinements, optimizing design workflows.
Design Engineer, Research Group
Processware Systems
02.2021 - 02.2022
- Designed and validated digital circuits for defense applications, adhering to DO-254 standards for high-reliability systems.
- Utilized Xilinx Vivado for FPGA design and verification, optimizing performance for real-time signal processing tasks.
Technical Intern, Standard Cell Department (TDP/TRND)
STMicroelectronics
06.2019 - 05.2020
- Spearheaded the complete backend flow for library generation, characterizing standard cell libraries for 28nm processes to deliver accurate timing, power, and noise models.
- Conducted Power, Performance, and Area (PPA) analysis of standard cell flip-flops, optimizing designs for improved efficiency and performance in 28nm technologies.
- Executed comprehensive physical design flow, including floorplanning, placement, clock tree synthesis (CTS), and routing, ensuring manufacturable and high-performance IC layouts.
- Performed static timing analysis (STA) across multiple PVT corners, verifying design timing constraints to ensure robust performance and reliability.
- Analyzed IR drop and timing models (NLDM), contributing to accurate ECO and CORE cell placement on floorplans at varying frequencies.
Skills
- EDA Tools: Cadence (Virtuoso, Spectre, Liberate, Innovus), Xilinx Vivado, Mentor Graphics (Eldo, Kronos)
- Hardware Description Languages: Verilog
- Scripting & Automation: TCL, Shell Scripting
- Operating Systems: Linux/Unix
- IC Design Expertise: Standard Cell Characterization, Physical Design Flow, Physical verification flow
- Soft Skills: Problem-Solving, Teamwork, Client Communication
Education
M.TECH - VLSI DESIGN
National Institute of Technology Delhi
Delhi 08.2018 - 07.2020
Timeline
Senior Application Engineer
Cadence Design Systems
02.2022 - Current
Design Engineer, Research Group
Processware Systems
02.2021 - 02.2022
Technical Intern, Standard Cell Department (TDP/TRND)
STMicroelectronics
06.2019 - 05.2020
M.TECH - VLSI DESIGN
National Institute of Technology Delhi
08.2018 - 07.2020
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