Karthik Ramaswamy
Senior Technology Leader Design For Test
Bangalore
Summary
Contribute to a technical leadership role in a organization.
๐๐๐๐จ๐ค๐ฃ๐๐ ๐ฟ๐๐ (๐ฟ๐๐จ๐๐๐ฃ ๐๐ค๐ง ๐๐๐จ๐ฉ) ๐ฉ๐๐๐๐ฃ๐ค๐ก๐ค๐๐๐จ๐ฉ ๐ฌ๐๐ฉ๐ 24+ ๐ฎ๐๐๐ง๐จ ๐๐ง๐๐ซ๐๐ฃ๐ ๐จ๐๐ข๐๐๐ค๐ฃ๐๐ช๐๐ฉ๐ค๐ง ๐๐ฃ๐ฃ๐ค๐ซ๐๐ฉ๐๐ค๐ฃ ๐๐ง๐ค๐ข ๐๐ค๐ฃ๐๐๐ฅ๐ฉ ๐ฉ๐ค ๐ฅ๐ง๐ค๐๐ช๐๐ฉ๐๐ค๐ฃ. ๐ ๐๐ง๐๐๐๐ฉ๐๐๐ฉ ๐ง๐ค๐๐ช๐จ๐ฉ ๐ฉ๐๐จ๐ฉ ๐จ๐ค๐ก๐ช๐ฉ๐๐ค๐ฃ๐จ ๐ฉ๐๐๐ฉ ๐ง๐๐๐ช๐๐ ๐๐ช๐จ๐ฉ๐ค๐ข๐๐ง ๐ง๐๐ฉ๐ช๐ง๐ฃ๐จ, ๐๐๐๐๐ก๐๐ง๐๐ฉ๐ ๐ฉ๐๐ข๐-๐ฉ๐ค-๐ข๐๐ง๐ ๐๐ฉ, ๐๐ฃ๐ ๐๐๐ก๐๐ซ๐๐ง ๐ข๐๐๐จ๐ช๐ง๐๐๐ก๐ ๐๐ค๐จ๐ฉ ๐จ๐๐ซ๐๐ฃ๐๐จ ๐๐ค๐ง ๐๐ฃ๐๐ช๐จ๐ฉ๐ง๐ฎ-๐ก๐๐๐๐๐ฃ๐ ๐ค๐ง๐๐๐ฃ๐๐จ๐๐ฉ๐๐ค๐ฃ๐จ ๐๐ฃ๐๐ก๐ช๐๐๐ฃ๐ ๐ฝ๐ง๐ค๐๐๐๐ค๐ข ๐๐ฃ๐ ๐๐๐๐-๐๐ง๐ค๐ฌ๐ฉ๐ ๐จ๐๐ข๐๐๐ค๐ฃ๐๐ช๐๐ฉ๐ค๐ง ๐จ๐ฉ๐๐ง๐ฉ๐ช๐ฅ๐จ
Overview
25
25
years of professional experience
Work History
DFT Consultant
Fermi Silicon Designs Private Limited
11.2024 - Current
- Provided specialized DFT consulting services at Meta for three months, focusing on establishing robust block-level DFT implementation flows.
- Developed DFT macro-RTL and executed synthesis processes for block-level designs.
- Architected and implemented comprehensive ATPG (Automatic Test Pattern Generation) flow setup.
- Conducted netlist analysis and test coverage estimation to ensure optimal fault detection and design testability metrics.
DFT Lead - Global Team
Rivos Inc
04.2024 - 10.2024
- Led distributed DFT engineering team across Taiwan, US, and Bangalore offices, coordinating complex AI chip development activities and ensuring seamless collaboration across time zones and cultural boundaries.
- Executed hands-on SSN top-level retargeting and bringup activities for complex AI processor.
- Conducted comprehensive lessons learned analysis with cross-functional team following A0 silicon evaluation, identifying key improvement opportunities and providing actionable recommendations that directly informed B0 product architecture decisions.
- Evaluated and validated Real Intent DFT tools for RTL-level DFT Design Rule Check (DRC) implementation that reduced downstream tapeout risks by catching design issues at RTL phase.
DFT Practice Head
L&T Technology Services
06.2023 - 03.2024
- Led a 65-member DFT team comprising primarily junior engineers with 1-3 years of experience.
- Managed comprehensive responsibilities including team training, recruitment, and direct client interactions.
- Delivered 8-week intensive DFT training programs to onboard junior engineers for client-ready project work.
- Guided engineers in advancing their ATPG (Automatic Test Pattern Generation) and MBIST (Memory Built-In Self-Test) technical capabilities.
- Provided ongoing mentorship and career development support to engineering team members.
- Established training frameworks that successfully transitioned junior talent into productive client-facing roles.
Director of Engineering
Marvell India
08.2020 - 04.2023
- Company Overview: As part of Marvell acquisition of Skandysys startup
- Played a pivotal role in building a 40-member DFT team that became a key strategic asset in Marvell's acquisition decision.
- Managed comprehensive team operations including stabilization, empanelment, technical execution, recruitment drives, and P&L accountability for the DFT group.
- Successfully transformed a struggling startup organization and strategically positioned it for successful acquisition.
- Oversaw end-to-end complex DFT execution processes from initial implementation through silicon bringup phases.
- Led team in executing critical pattern debugging activities to ensure design-for-test quality and functionality.
- Demonstrated leadership in turning around organizational challenges while maintaining technical excellence and financial performance.
- As part of Marvell acquisition of Skandysys startup
R&D IC Design Engineer
Broadcom Inc
04.2012 - 08.2020
- Served as DFT lead for advanced 16nm and 7nm semiconductor designs, managing complex technology node requirements.
- Executed hands-on technical work across multiple DFT domains including Scan Insertion, MBIST Insertion, JTAG, simulation workflows, DDR, SerDes integration, IO, and PLL programming.
- Led comprehensive DFT implementation from initial architecture through full production for 2 large-scale designs exceeding 400 square millimeters.
- Managed end-to-end DFT execution covering both scan and memory built-in self-test simulations for complex multi-million gate designs.
- Presented technical innovations at APD forums, specifically showcasing customized DDR IO handling methodologies and implementation flows.
DFT Manager
Smart Play Technologies
01.2011 - 03.2012
- Implemented programmable MBIST solutions and conducted comprehensive memory verification for test chips, ensuring successful tapeout delivery.
- Successfully executed end-to-end IO test chip development and achieved multiple successful tapeouts with verified functionality.
- Led hands-on verification activities for memory subsystems, validating test coverage and diagnostic capabilities across various memory types.
- Managed complete test chip flow from design implementation through silicon validation, demonstrating proven tapeout success record.
- Provided technical mentorship and guidance to junior team members, fostering skill development in MBIST and test methodologies.
IC Design Engineer
Broadcom Singapore
03.2008 - 01.2011
- Established and implemented comprehensive memory compilation flows, enabling automated memory generation and integration processes.
- Developed memory repair analysis methodologies and implemented repair solutions to improve silicon yield and functionality.
- Set up complete Logic Vision (LV) flow encompassing Scan, MBIST, JTAG, and LV-TK integration for comprehensive DFT coverage.
- Executed DFT insertion for 40nm technology node chip featuring high memory and clock density across ~180 square millimeter design area.
- Performed detailed clock and reset domain analysis using Logic Vision tools, identifying and resolving timing and functional issues.
- Collaborated closely with design teams to address clock/reset interaction challenges and ensure successful DFT implementation in complex memory-intensive designs.
Component Design Engineer
Intel India
12.2005 - 02.2008
- Managed complete fuse design implementation and validation processes, ensuring reliable programmable functionality across silicon designs.
- Executed end-to-end ECO (Engineering Change Order) flow including RTL enhancements, structural changes, netlist modifications, and formal verification.
- Conducted comprehensive functional validation for fuses and straps, verifying programmability and retention characteristics across operating conditions.
- Delivered formal verification and model releases ensuring design integrity and compatibility throughout the ECO implementation cycle.
- Maintained complete ownership of critical DCNs (Design Change Notices) and provided timely resolution of complex bug fixes.
Senior Design Engineer
Wipro Technologies
09.2003 - 12.2005
- Implemented at-speed testing using Launch-from-Capture methodology, enabling comprehensive timing validation across multiple operating frequencies.
- Delivered test vectors for diverse clock domains through sophisticated PLL control mechanisms, ensuring proper at-speed test coverage.
- Developed and evaluated memory repair solutions utilizing Genesys Array test maker platforms for enhanced yield optimization.
- Architected comprehensive test strategies for complex multi-domain chips, balancing coverage requirements with test time constraints.
- Conducted advanced tool evaluations focused on test volume reduction techniques and next-generation memory repair methodologies.
Staff Engineer
Purple Vision Technologies
06.2000 - 09.2003
- Rapidly acquired DFT concepts and expertise, contributing as part of a 4-member founding team that established the TI account for Purple Vision.
- Helped develop the TI account from startup phase into the company's largest and most significant client relationship.
- Mastered industry-standard DFT tools including DFT Advisor, Fastscan, and Synopsys toolchain for comprehensive design-for-test implementation.
- Successfully applied newly acquired DFT knowledge across multiple design projects, demonstrating quick learning and practical application capabilities.
Education
Masters - Microelectronics
Manipal University
01.2012 - 1 2014
BE - Electronics & Communication
M.S University
01.1995 - 1 1999
Executive General Management - undefined
IIMB
Skills
- Strong skills in design and validation
- Work experience in most DFT tool vendors and methodologies
- Hands-on experience in Scan Insertion, mbist insertion, DDR/Serdes integrations, IO planning
- Architected DFT for 16 nm and 7 nm designs
- Expert knowledge of DFT (both Analog and Digital), Verilog netlist debugging, SDF, functional and test simulations
- Expertise in atpg,memory repair simulations, atpg simulations
- Ability to work independently and also within a team
- Worked in more than 15 tape-outs till now
- Knowledgeable in Chip level Design/Integration activities
- Work closely with Verification Team to develop test plans and test cases
Tools
Verilog
Model Sim, VCS, Verilog XL
Mentor/Synopsys/Logic vision tools, DFT Advisor, Fastscan, Testkompress
MBIST Architect, Tessent toolset, DFT Compiler, Tetramax
Awards
- Received spark awards in Broadcom for flawless execution.
- Presented in APD worldwide group on customizations done in DDR and IOs for a complex 7 nm design.
- Served as President of IIMB Orators club in 2023 and recognized as exemplary leader.
Timeline
DFT Consultant
Fermi Silicon Designs Private Limited
11.2024 - Current
DFT Lead - Global Team
Rivos Inc
04.2024 - 10.2024
DFT Practice Head
L&T Technology Services
06.2023 - 03.2024
Director of Engineering
Marvell India
08.2020 - 04.2023
R&D IC Design Engineer
Broadcom Inc
04.2012 - 08.2020
Masters - Microelectronics
Manipal University
01.2012 - 1 2014
DFT Manager
Smart Play Technologies
01.2011 - 03.2012
IC Design Engineer
Broadcom Singapore
03.2008 - 01.2011
Component Design Engineer
Intel India
12.2005 - 02.2008
Senior Design Engineer
Wipro Technologies
09.2003 - 12.2005
Staff Engineer
Purple Vision Technologies
06.2000 - 09.2003
BE - Electronics & Communication
M.S University
01.1995 - 1 1999
Executive General Management - undefined
IIMB
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