Karthik S

Enthusiastic and organized VLSI engineer with 2 years of experience, passionate about VLSI design, verification, and development. Skilled in SoC/IP verification and eager to contribute and expand expertise across diverse VLSI domains.

• UVM, Cerium systems, 12/01/21
• DV Debug, Cerium systems, 12/01/21
• System Verilog, Cerium system, 10/01/21

TITLE:Design of Low Power Artificial Hybrid Adder using Neural

Network for energy efficient arithmetic operations:

Description: Developed an energy-efficient hybrid adder using Artificial Neural Networks,

focusing on minimizing energy-delay product (EDP) for arithmetic applications.

Technologies & Tools: FPGA, Xilinx Vivado, Verilog, Neural Networks

TITLE: High-Speed Hybrid-Logic Full Adder Using 10-T XOR-XNOR Cell

Designed a hybrid logic full adder incorporating an optimized XOR-XNOR circuit to improve speed and power efficiency. The approach enhances overall circuit performance, making it suitable for low-power and high-speed arithmetic applications. Simulated and verified using industry-standard tools.

Tools & Technologies Used: Cadence Virtuoso, CMOS Technology(90nm).

Name: Karthik S

D.O.B: 06-12-1998

Gender: Male

Father’s name: Sathyapal Bhandary

Mother’s name: Sharmila Bhandary

Languages Known: English, Kannada, Hindi, Tulu

Nationality: Indian