Karthik Sanjay Raj Varma CA

Bengaluru

Summary

Skilled Digital IC Design Engineer with over 2 years of experience in developing high-performance integrated circuits. Expertise in collaborating with modem and interconnect design teams for 3nm projects, delivering timing clean netlists, and working with cross-functional teams during synthesis and TECO cycles to ensure effective digital design implementation.

Overview

years of professional experience

Work History

SENIOR ENGINEER (STA/Synthesis)

MediaTek

Bengaluru

07.2023 - Current

Performed static timing analysis(STA) for two designs
Projects: (CHI / 3nm / 1.6Ghz), (Modem 4-6nm / 19 partitions /1.2 Ghz /~40M Inst)
Full Ownership of STA env at Top level for both CHI and Modem
Cleared blackbox and signal level violations while maintaining multi voltage domain settings for all DVFS corners.
Performed Correlation between SOC and MD for any mismatch.
Collaborated with APR team to fix timing issues and ensure timely release of SPEF, TECO TCL, and action items across multiple TECO cycles.
Executed synthesis for three projects
Synthesized high frequency designs in multi corner multi-mode environments.
Collaborated with PD teams to analyze and resolve congestion and timing violations during synthesis, optimize region placement and achieve good synthesis-APR correlation.
Resolved congestion through various techniques, leading to notable improvements in power performance and area (PPA) for critical blocks.
Top preSTA owner for Modem.
Implemented FECOs to address QC issues and meet PPA standards.

Engineer

LTTS

Bangalore

08.2019 - 03.2021

Operated as a contract worker for INTEL, supporting various projects.
Executed manual testing on RVP's for modem chipset to ensure functionality.
Performed stress testing on RVP's to assess reliability and stability.

Education

M.E - Embedded Systems

BITS Pilani Goa Campus

Goa

07-2023

B.Tech - Electronics And Communications Engineering

JNTUH College of Engineering

Hyderabad

05-2019

Skills

Static Timing Analysis: Primetime, Tweaker
Synthesis: Genus ,Design Compiler ,Tcl

QC: LEC, DRC, ERC, CLP

Hobbies and Interests

Bike enthusiast
Badminton
Trekking

Languages

English, Hindi, Telugu

Timeline