Over 4.5 years of expertise in designing and integrating subsystems at ASIC SoCs.
I am ready to explore new areas of emerging technologies and have a quick response to new spheres. I am committed to delivering high-quality SoC solutions.
Area of application: Mobile SoC.
Task: Serial interface (I2C, SPI, UART).
Block ownership: Integrating IPs to get a functional block and generating RTL using flow.
Compilation for the generated RTL.
Generating memories for the block.
Performing minimum period checks for memories.
Inserting MBIST for memories.
Lint check for generated RTL.
Introducing the simulation environment to the block.
Checking the RTL, whether it is synthesizable or not.
DFT check for scan coverage analysis.
Maintaining design documents, clock, and power diagrams
CDC and GLS cleanup
FECO for bug fix after RTL freeze
collaborating with IP owners, DV, PI, and DFT teams.
DMA IP Task:
PDMA and SPDMA IP handling and debugging for issues at the block level.
Responsibilities and Achievements: -
Block ownership: Integration of peripheral blocks.
Worked on Spyglass LINT and Spyglass DFT. Added constraints to obtain coverage in DFT.
Worked on JASPER AFL and XPROP tools to check formal linting and X-propagation. • Worked on Meridian Intent CDC.
Secured AIR 929 in GATE 2017, conducted by IIT Roorkee