Keshave K

Results-driven Physical Design Engineer with 3+ years of experience specializing in low-power design methodologies and wireless communication systems. Proficient in designing and implementing complex ASICs/SoCs, with a focus on optimizing power consumption while maintaining high performance. Skilled in leveraging industry-standard tools and protocols to develop innovative solutions that meet stringent requirements. High-performing Design Engineer with solid background in software engineering. Skilled in using CAD software, prototyping and testing with keen eye for detail. Proven ability to lead cross-functional teams in design, development and implementation of complex projects. Creative and innovative prospect determined to bring ideas to life through cutting-edge technology and design techniques. Team player with strong problem-solving skills to contribute effectively to projects and teams. Considers unique and unconventional solutions to deliver exceptional results.

• Genus
• Innovus
• Aprisa
• oasys
• Tempus
• Voltus
• calibre
• Questa sim
• Vivado
• Vitis hls
• Matlab
• 28nm
• 22nm
• 16nm

Project Title : AI-chip

Description : Equipped with an Arm Cortex M0 processor and a HiFi 3 DSP to support feature extraction and signal processing for image and voice enhancements, the NDP250’s integrated power management unit allows single power rail operation, where the integrated phase-locked Loop (PLL) provides further system cost and size optimization.

With the ability to process multiple heterogeneous networks concurrently, the NDP250 also supports convolution neural networks including 1D, 2D and depth-wise, fully connected networks, and recurrent neural networks including LSTM (long short-term memory) and GRU (gated recurrent unit).

Technology node : TSMC 22nm

Client : Syntiant Corp

Roles and Responsibilities : Responsibility includes Timing Analysis, Timing ECO generation for segregated mode timing corners. The product is a flip chip low power SOC, 22nm silicon with core operating at 120Mhz.

Faced timing challenges such as huge functional data-paths, bad clock-skew imbalances, late discovery due to missing constraints and the slack impact, low power impact, CLP issues, Timing Signoff confirming to TSMC 22nm.

Analysed specified functional/scan  modes timing reports and derived timing ECOs for closure.

Used a self-scripted Timing-ECO generation flow parsing uniquified timing-path-reports for quick ECO generation using TCL, Shell commands and perl and ECO iteration towards convergence.

Project Title : CXL-IP Hardening

Description : This project was a block-level implementation of a CXL design. The system consists of a CXL core and peripheral logics. The desired frequency for the block was 1GHz, with a total instance count of
700k+. The desired technology node is 28 nm. The design featured DFT.
structures are inserted, creating four alternative constraint modes.
(Functional, Shift, Capture, and MBIST) for the design to close on. 

Technology node : TSMC 28nm

Client : Mobiveil

Roles and Responsibilities :  Responsibility include Floorplanning for 396 Macros and Timing Signoff with timing eco lic flow and LEC signoff.

faced macroplacement , congestion, signal integrity, crosstalk, timing challenges such as snake paths  from top to blocks, TSMC eco signoff flow.

used self-scripted Macro placement script, which places module wise and it is timing driven, automated scripts for design quality and metric generation, scripted selection of buffers, and gates from library which  enhances the PBA timing.

Project Title : Low power IOT device

Description : This is a highly intricate low-power block exceeding 700k instances,
and 8 macros. It had 9 distinct power domains, 4 of which were
switchable for optimized power consumption and 5 of which are
varying voltage thresholds.

Technology node : 16nm

Client :  Lattice Semiconductor

Roles and Responsibilities : Responsibility includes, synthesis with UPF, LEC, CLP, PNR and EM-IR signoff 

faced isses in UPF validation, Power domain and Power structure, redundant placement of back to back levelshifters, IR drop. used low power validation self scripts for placement of powerswitches and power connectivity, Electrical rule checkers and proper levelshifter placement, voltage island generation scripts. 

• Awarded with the Brilliant Groundbreaking for contributions to Automatic Reverse parking Algorithm in Automotive VLSI.