Kevin Sathya Seelan

Innovative Device Engineer with a substantial background in the design, development, and optimization of various electronic devices. Strengths include comprehensive knowledge of device fabrication processes, semiconductor physics, and integrated circuit technology. Proven track record in delivering successful projects on time and within budget, while maintaining the highest quality standards. Contributed significantly to the previous work environment by optimizing existing designs for improved performance and efficiency.

• Certificate of Recognition, 04/01/21, awarded Certificate of Recognition at Microchip for optimizing the MIC2129 PWM 100V COT controller, improving the overall device selection from various process technologies
• Leadership and collaboration: Led a team of six in developing and presenting a business proposal to the vice president and director of Microchip, showcasing strong leadership and collaboration skills
• Community service, contributed to sorting over 30,000 pounds of produce quarterly for Second Harvest of Silicon Valley as part of a 30-member cross-functional team, demonstrating commitment to community service and teamwork
• Proficiency Award, holds merit for receiving the Proficiency Award for 'Outstanding Student of the Year' for discipline, sports, and education

Design and fabrication of Microstrip Coupled Line Filter, Keysight ADS, 11/01/21, Designed 3rd order microstrip coupled line Chebyshev Bandpass filter for 3 GHz and observed attenuation at 2.45 GHz and obtained low insertion loss, attenuation using tapers in ADS and EM simulations. The design with best Figure of Merit was fabricated and a comparison was made between Circuit and Schematic simulation along with the EM simulation for verifying the schematic level design. Design and Implementation of a Microstrip Impedance Matching Circuit, Keysight ADS, 10/01/21, Designed and optimized a microstrip open stub circuit using ADS, improving impedance matching. This Project helped in the implementation of stub matching network like Single stub, pi Configuration and multi stub matching Network with an additional experience of learning techniques to increase the bandwidth. It also provided experience in generating a layout and validated schematic-level designs through full-wave EM simulations, ensuring signal integrity and bandwidth optimization. 6T SRAM, Cadence Virtuoso, Implementation of 6T SRAM cell from scratch and verifying the DRC, LVS and parasitic extraction. Used H-Spice as an aid to find the performance of the SRAM cell.