Khausik S

Experienced VLSI professional skilled in RTL design and verification using Verilog, System Verilog, and UVM. Proficient in developing testbench code and ensuring comprehensive functional coverage. Strong background in digital design principles and expertise in EDA tools and protocols. Dedicated to ongoing growth, eager to learn new skills and stay updated with industry advancements.

HDL : Verilog
HVL : System Verilog
Protocols : APB, AHB, AXI,SPI
Verification Methodologies: UVM
Domain : ASIC Verification
Knowledge : Digital Electronics, Verilog, System Verilog and UVM

Verification of Memory Map Integration in SOC
Language: C++
Tools: QuestaSim
Description:
Ensuring the memory map fits seamlessly into the SOC design, assign in memory regions and device interfaces accurately.
My Role:
Learned the SOC verification process and requirements.Developed detailed plans covering various memory access scenarios.Created test cases for different memory operations and boundary conditions.Worked closely with design engineers to align verification with memory map specifications.

Verification of JTAG IEEE std 1149.1

Language : System Verilog (Universal Verification Methodology)
Tools:  QuestaSim
Description:
JTAG, which stands for "Joint Test Action Group," is a widely used industry- standard protocol and technology primarily used for testing and debugging integrated circuits during manufacturing and in-system testing.JTAG provides a standardized way to access and control the internal components of digital ICs, even when they are embedded in a larger system. It allows for testing the interconnections between different components on a printed circuit board or within an IC itself.
My Role:  
Developing the testbench architecture and UVM components.Verified it by writing assertions.

Verification of USB 2.0 Host Controller
Language : System Verilog (Universal Verification Methodology)
Tools: QuestaSim
Description:
SOC level verification of USB 2.0 Host Controller integrated in RISC-V architecture based SOC. Verification to ensure the integration of host controller to the SOC and its functionality.
My Role:  
Understood the SOC level verification process and planning for verification.Participated in test-case generation (Enumerating the device, 3 modes of transfer).Verified the functional coverage.