Khushi Verma

• Utilized EDA software such as Synopsys Design Compiler and PrimeTime to synthesize RTL into gate level netlists with timing constraints.
• Hands on experience on Spyglass, Vcspyglass to perform QA checks.
• Built FW_1.6 patch of Intel and AMD
• Worked on 2 projects: Synopsys MIPI-MPHY n423_c20_ss5lpe and
  n440_c20_tsmc3pff.
• Worked on constraint validation using Primetime constraint checker and timing analysis.

·Interned at ChipSpirit Technologies as a design and verification engineer from May’23 to July’23

·Completed Internship at Maven Silicon and attained a basic knowledge of VLSI Design flow, Verilog Programming (Coding the design and writing testbenches}