Xilinx Vivado
KIRAN J PURAD
Design and Verification Engineer
Bengaluru
Summary
To excel as a VLSI engineer by enhancing my skills and experience towards organization growth as well as my professional growth.
Overview
2
2
years of professional experience
8
8
years of post-secondary education
1
1
Certification
2
2
Languages
Work History
Intern
Maven silicon
Bangalore
10.2024 - 12.2024
- Designed and verified a 1x3 Router architecture using Verilog HDL to enhance data routing efficiency
- Gained hands-on experience in various tools like Modelsim and Quartus prime increasing proficiency and expanding technical skill set.
Design and Verification Engineer
Aricent Semiconductor Private Limited
Bangalore
06.2022 - 08.2023
- Worked as a Verification engineer for SmartDimming_SoftIP
- My role was to do Gate level simulation in FPGA design
- Recreate the existing simulation environment to validate the ASIC IP
Education
Mtech - VLSI Design And Embedded Systems
RV College of Engineering
Bangalore 01.2024 - Current
B E - Electronics and Communication Engineering
Bapuji Institute of Engineering And Technology
Davangere, India 08.2017 - 08.2021
PUC - Science
Alva's PU College
Mangalore 06.2015 - 05.2017
10th - CBSE
Sri Taralabalu Central School
Davangere 04.2014 - 03.2015
Skills
C
undefinedCertification
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite -Udemy
Software
ModelSim
Synopsys VCS
QuestaSim
Timeline
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite -Udemy
10-2024
Intern
Maven silicon
10.2024 - 12.2024
Mtech - VLSI Design And Embedded Systems
RV College of Engineering
01.2024 - Current
Design and Verification Engineer
Aricent Semiconductor Private Limited
06.2022 - 08.2023
B E - Electronics and Communication Engineering
Bapuji Institute of Engineering And Technology
08.2017 - 08.2021
PUC - Science
Alva's PU College
06.2015 - 05.2017
10th - CBSE
Sri Taralabalu Central School
04.2014 - 03.2015
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