KISHAN PAL

• CCK Check or ERC Checks
• Checks schematics for possible problems that may not be caught by simulation
• Used for Block and Chip Top pre-layout checking
• Allows cross-probing of reported violations to schematic.
• Client: Renesas

Project 1 : 100/200 mA DC-DC Buck Converter with

Hysteretic Mode Control.

• Client: MTRDC, DRDO – Bangalore.
• Technology: TSMC 40 nm CMOS.
• Tools used: Cadence, Virtuoso.
• Design and simulation of PSU modules for a hysteresis buck converter for an input supply of 3.6V, Vout of 1.2V, and a maximum load of 200mA.
• Description: 200 mA DCDC Buck Converter with Hysteretic Control includes Adaptive Hysteretic, Differentiator, OCP, ZCD, and LP Mode.

Project 1: 15 mA Low Dropout Regulator (on-chip LDO)

• Tools used: Cadence, Virtuoso.
• Technology: TSMC 28 nm CMOS.
• Design and verification of a 15 mA capless Low Dropout Regulator (LDO), supply of 1.8 V, and output voltage of 0.9 V.
• Various verifications are load regulation, line regulation, stability, PSR, and noise simulations.

Project 2: 50 mA Low Dropout Regulator (Capped LDO)

• Tools used: Cadence, Virtuoso.
• Technology: TSMC 40 nm CMOS.
• Design and verification of a 50 mA capped Low Dropout Regulator (LDO), supply of 1.8 V, and output voltage of 1.2 V.
• Achieved an accuracy of 5% in 3-sigma Monte Carlo variation.
• Various verifications are load regulation, line regulation, stability, PSR, and noise simulations.

Project 3: 0.7 V Bandgap Reference

• Tools used: Cadence, Virtuoso.
• Technology: TSMC 40 nm CMOS.
• Circuit Design and Verification of Bandgap.
• Description: The bandgap block contains an OTA with a PTAT and CTAT current network. Designed for a 0.7V output voltage with a 1.2V supply. PSRR of -85 dB at 10 kHz and -83 dB at 1 MHz achieved.