Summary
Overview
Work History
Education
Skills
Interests
Projects
Software
Timeline
Hi, I’m

Komal Deshmukh

Sr Analog Layout Engineer
Pune
Komal Deshmukh

Summary

Dynamic Full Custom Analog Analog Layout Design Engineer with a proven track record at Intel, excelling in mixed-signal layout and power distribution analysis. Recognized for enhancing team productivity through effective collaboration and innovative problem-solving. Successfully completed multiple tape-out projects, demonstrating strong time management and advanced layout techniques to improve design efficiency.

Professional with strong background in analog layout design. Adept at creating and optimizing circuit layouts, ensuring precision and functionality. Proven ability to collaborate effectively in team environments and adapt to changing project requirements. Skilled in CAD tools, and DRC/LVS verification, with focus on delivering high-quality results. Reliable team player known for achieving project milestones and contributing to innovative solutions.

Overview

11
years of professional experience
4
years of post-secondary education
3
Languages

Work History

Intel
Pune

Analog Layout Design Engineer
08.2014 - Current

Job overview

  • Assisted junior engineers in understanding critical aspects of analog layout techniques, fostering a collaborative work environment.
  • Delivered optimal solutions for complex routing problems through meticulous planning and innovative approaches.
  • Managed project timelines effectively, ensuring on-time delivery of high-quality layouts that met customer requirements.
  • Collaborated with cross-functional teams to resolve design issues, ensuring successful takeouts.
  • Reduced design cycle time with effective floor planning and placement strategies for complex circuits.
  • Proactively identified opportunities for process improvement, leading to enhanced efficiency in the design flow.
  • Enhanced team productivity by providing training on advanced layout tools and methodologies.
  • Completed extensive research on specific issues and compiled reports with findings.
  • Participated actively in team meetings and provided valuable input towards enhancing overall project execution strategies.
  • Successfully completed multiple tape-out projects by adhering to strict quality standards and design specifications.
  • Improved design efficiency by implementing automation techniques in analog layout processes.

Intel
Bangalore

Layout Intern
02.2014 - 08.2014

Job overview

  • Supported staff members in their daily tasks, reducing workload burden and allowing for increased focus on higher-priority assignments.
  • Gained valuable experience working within a specific industry, applying learned concepts directly into relevant work situations.
  • Analyzed problems and worked with teams to develop solutions.
  • Contributed to a positive team environment by collaborating with fellow interns on group projects and presentations.

Education

BITS PIlani
Pilani

Master of Technology from Microelectronics
12.2017 - 12.2019

University Overview

University Of Pune
Pune, India

Master of Science from VLSI , Electronics Science
08.2012 - 08.2014

University Overview

Skills

Mixed-signal layout

Interests

Custom Routes , Power Grid analysis , Reliability , RV , EM, IR

Projects

Projects
Voltage Stack IP [Ribbon FET, Backside Metals Technology] | Layout Lead
  • Independently owned and executed the layout as a single MD owner, ensuring the successful delivery of the entire layout.
  • Designed and implemented various hierarchies of CBBs (Common Building Blocks) in Voltage Stack IP layout design.
  • Developed and delivered Level Shifters and Resistor Dividers, meeting design specifications.
  • Led the generation and optimization of MIM (Metal-Insulator-Metal) power grids at the top level, achieving significant performance improvements.
UCIe-Advanced (Universal Chiplet Interface Express) 18A (Intel Process) | Layout Lead
  • Developed comprehensive layout plans for analog circuits, considering factors like power distribution, signal integrity, and thermal management.
  • Collaborated with circuit designers to optimize layout for performance and manufacturability.
  • Coordinated with the overall chip floorplanning team for efficient analog block placement.
  • Designed and verified power distribution networks to minimize voltage drops and noise.
  • Conducted DRC, LVS checks, and collaborated with designers to resolve issues.
  • Led a team of analog layout engineers, providing mentorship, guidance, and technical oversight to meet project milestones.
DTS (Digital Thermal Sensor) 7nm Thick Gate (Intel Process) | Layout Tech Lead
  • Managed and reviewed DTS layout designs, ensuring strict adherence to design rules and specifications.
  • Designed and optimized thick gate BGR layouts for improved performance and manufacturability.
  • Conducted rigorous verification for DRC, LVS, RV, and ESD flows to ensure compliance.
  • Provided mentorship to junior engineers and contributed to the overall design review process.
DDR 7++nm (Intel Process) | Analog Layout Engineer
  • Focused on layout optimization, area reduction, and pin ring closure for DDR transmitter designs.
HBMIO (8Gbps) 7++nm (Intel Process) | Analog Layout Engineer
  • Managed layout migration from 7nm to 7++nm node.
  • Implemented design changes with minimal area impact.
  • Optimized capacitance and routing for clock distribution blocks.
  • Converted single LDO to micro LDO for enhanced efficiency.
HBMIO (6.4Gbps) 7nm (Intel Process) | Analog Layout Engineer
  • Developed and modified layouts for Analog IPs like LDO, MDLL, ViewAna, global clock distribution, and VREF.
  • Executed end-to-end development of layouts in Intel 7nm node with a focus on area constraint management, RV, and ESD compliance.
  • Designed single on-chip LDO with a 240mA load current requirement, optimizing for area and IR drop.
  • Co-authored a paper on LDO design challenges.
  • Developed layouts for error amplifiers, Biasgen, and current mirror circuits, ensuring device matching and thermal management.
  • Implemented ESD protection circuitry with optimized pad capacitance and ballast resistance.
  • Provided mentorship to junior engineers and managed assignments.
  • Led SoC-level custom routing for IR drop analysis and parasitic impact improvements.
Gen3Phy (10nm Intel Process) | Analog Layout Engineer
  • Designed and verified clock distribution AIP layouts.
  • Managed DFE and CTLE layout verification and clean-up.
  • Developed customized device templates to enhance capacitance and resistance matching.
  • Implemented innovative common centroid layouts and source degeneration sharing, achieving a 22% gain boost in CTLE performance and 6% bandwidth improvement in folded stages.
SoC Layout Support (10nm/14nm/22nm Intel Process) | Layout Engineer/Mask Designer
  • Conducted layout verification in ICC across multiple nodes.
GPIO 14nm (Intel Process) | Layout Engineer/Mask Designer
  • Created top metal (TM) templates for different layout orientations.
  • Designed and verified GPIO layouts using automation flows in GeneSys, collaborating with the DA team to enhance automation efficiency.

Software

Cadence Virtuoso XL, Totem RV,

Timeline

BITS PIlani
Master of Technology from Microelectronics
12.2017 - 12.2019
Analog Layout Design Engineer
Intel
08.2014 - Current
Layout Intern
Intel
02.2014 - 08.2014
University Of Pune
Master of Science from VLSI , Electronics Science
08.2012 - 08.2014

Similar Profiles

  • Amani Elmagdub

    Amani ElmagdubAmani Elmagdub

    Manufacturing Technician at IntelManufacturing Technician at Intel

    View Profile
  • Gustavo Garcia

    Gustavo GarciaGustavo Garcia

    Pipefitter Leadman at IntelPipefitter Leadman at Intel

    View Profile
  • Leonard Okeke

    Leonard OkekeLeonard Okeke

    Module Technician at IntelModule Technician at Intel

    View Profile
Komal DeshmukhSr Analog Layout Engineer