Komal Udai
Bengaluru
Summary
A proficient professional with one year of full-time experience in PDK development, skilled in Python automation for relevant projects, and knowledgeable in Object-Oriented fundamentals. Additionally, have internship experience at Intel Corporation as a Design Verification Intern, where I gained foundational skills in System Verilog and UVM.
Overview
2
2
years of professional experience
Work History
Research and Development Engineer
Keysight Technologies
05.2023 - Current
- Engaged in automating EM qualification flow for various foundries, focusing on ADS..This involved importing GDS, setting up projects, and executing RFPro Momentum simulations
- Additionally, automated processes were implemented to generate layout database files, export EM simulated data, and post-process to extract device under test (DUT) parameters
- PDK Development: Understanding of callbacks and PCell development in AEL(Application Extension Language) in ADS(Advanced design Systems).Familiar with DRC and LVS.
Design Verification Intern
Intel Corporation
06.2022 - 05.2023
- Collaborated closely with the DFx team to integrate Boundary Scan/JTAG techniques.Methodically designed and executed thorough testbenches to guarantee seamless RTL design verification
- Participated in the development of a DFD module within the subsystem, ensuring its functionalities such as trigger, trace, and memory access were thoroughly tested and debugged
- Skilled at issue diagnosis, regression analysis, and utilizing tools like Synopsys VCS and Verdi.
Education
M.Tech - VLSI System Design
National Institute Of Technology
Warangal, India06.2023
B.Tech - Electronics And Communications Engineering
SardarVallabhbhai National Institute of Technology
Surat05.2018
Intermediate/+2 - PCM
DDSM Sr. Sec School, RBSE
Ajmer, India05.2013
Skills
- Programming Language: Python, C, C
- Hardware Description/Verification Language: Verilog ,System Verilog
- OS: Windows, Linux
- Tools: ADS ,Synopsys VCS, Verdi, Cadence Virtuoso, Vivado Design Suite
Areas Of Interest
- PDK Development
- RTL/Digital Design
- Design Verification
Academic Projects
Performance Analysis Of Vertical Tunnel FET :
- Developed conventional VTFET structure using only Si as device material in Sentaurus TCAD Tool.
- To get the better device performance developed and simulated different structure i.e. Ge Pocket Vertical TFET, Ge/Si HJ-Vertical TFET.
- Further to increase the ON current of proposed device with Dual Gate Material and using pocket engineering.
Implementation of Advanced Encryption Standard algorithm:
- Developed the Top module for 128-bit AES algorithm for encryption and decryption in verilog and in addition to that developed HDL module for its key generation in Verilog.
- Implemented and synthesis of the module on ARTIX board with the help of Vivado Tool.
Timeline
Research and Development Engineer
Keysight Technologies
05.2023 - Current
Design Verification Intern
Intel Corporation
06.2022 - 05.2023
M.Tech - VLSI System Design
National Institute Of Technology
B.Tech - Electronics And Communications Engineering
SardarVallabhbhai National Institute of Technology
Intermediate/+2 - PCM
DDSM Sr. Sec School, RBSE
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