Summary
Overview
Work History
Education
Skills
Additional Information
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Komala M

Vlsi layout Design Engineer
Bangalore,Karnataka

Summary

I have always believed that development in technology is the solution for many day-to-day problems and I have been working towards being a part of that development since I took Electronics Engineering as my major. That led to previous experiences and currently positioned as Analog layout design engineer at Wipro Ltd. I am passionate towards working in the field of Silicon manufacturing, particularly in the field of Layout design and development.

Overview

5
5
years of professional experience
4
4
years of post-secondary education

Work History

Analog Layout Design Engineer

Wipro Ltd
Bengaluru
04.2021 - Current
  • 4.5 Years of Experience as VLSI engineer with relevant experience of 3 years in Analog layout designing.
  • Hands-on experienced Layout designing tools like cadence virtuoso, Genesys,
  • ICC2, Physical verification tool Calibre and ICV
  • Worked with INTEL and also recently worked with Omni Design Technologies
  • Worked in Finfet Technology 14nm ,10nm,7nm and 6nm
  • Trained and worked as Physical Verification Engineer over a period
  • Hands on experience in Floor Planning and Layout of various analog IP like PLL,
  • Opamps, Serdes and Digital blocks in Process Monitor etc
  • Proficient physical verification in DRC, ERC and LVS debugging
  • Implemented concepts like Matching, Shielding, Guarding placement etc
  • Worked on some basic RV fixes.

Analog Layout Design Engineer

Altran technologies (Capgemini)
Bangalore
04.2018 - 12.2021

Education

Electronics and Communication

VTU
Davangere
08.2013 - 07.2017

Skills

Layout editor :Virtuoso L&XL, Genesys

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Additional Information

Process Monitor

  • Designed Digital blocks like counter 10b and counter 2b . Designed RO Logic block that is used in Ring Oscillator.
  • Responsibilities: Analysis of EM&IR . As it is IR sensitivity taken care in Floor planning with Area constraint . IR drop was taken care by developing proper power mesh formation. Taken care of the parasitic in the initial layout design to avoid more iteration in post layout tunning Most challenging part was Power mesh creation in Digital block with lower metals. Density fill specially OD_PO fill , EM check and Parasitic Extraction are done .

PLL (Charge Pump)


  • Responsibilities: Floorplan, Routing and Verification for charge pump. Taken care in routing the UP and DOWN signals and working with designer to reduce the mismatches. Matching for the Differential amplifiers and current mirrors are taken care. Taken care routing Current signals and Voltage signals. Latch-up and Antenna fixes. Taken care in routing of clock nets and maintained exact symmetry between clock signals.

Serdes (Tx Block)

  • Responsibilities :Area estimation, Floor plan and LEF creation. Latch-up and Antenna fixes. Maintained good enough metals to have appropriate output resistance. Taken care in Routing clock signals and shielding is used for critical signals. DRC and LVS checks.

Opamp and Level Shifter

  • Responsibilities: Floor Planning and Routing. The Level shifter is designed to support 1.1 V to 1.8 V signaling Taken care in routing of clock nets and maintained exact symmetry between clock signals. Latch-up and Antenna fixes. Matching is done for current mirror and differential pair. DRC and LVS checks .

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Komala MVlsi layout Design Engineer