KOUSHIK M T
VLSI Design Intern
Bengaluru,Karnataka
Summary
VLSI Design Intern with hands-on experience in RTL design, verification, and digital hardware development. Seeking opportunities in RTL Design and Design Verification to contribute to high-quality semiconductor products and enhance technical expertise.
Overview
1
1
year of professional experience
3
3
Certification
Work History
Graduate Technical Intern
Intel
06.2025 - 05.2026
- Designed a traffic controller with priority-based arbitration and mutual exclusion, and performed RTL quality checks using FPV and Superlint across multiple clock domains.
- Performed formal verification of IP ULT blocks using SystemVerilog Assertions (SVA), developing and debugging properties and assumptions to validate functional correctness and corner cases, and supporting RTL debug.
- Worked on post-processing checkers in SysIP emulation to verify protocol compliance and transaction ordering using emulation-generated traces, enabling efficient failure triage and RTL root-cause analysis.
Education
M.E. - Microelectronics and VLSI Technology
MSIS MAHE
06.2026
B.E. - Electronics and Communication Engineering
JNNCE VTU
05.2024
Skills
- Verilog HDL
- SystemVerilog
- SystemVerilog Assertions (SVA)
- UVM
- Python
- TCL
- Cadence JasperGold
- Cadence Virtuoso
- Arduino IDE
- Scilab
- Intel Quartus Prime
- Genus Synthesis Solution
- Xilinx Vitis 2023
Certification
- SystemVerilog Assertions Basics - Udemy
- Verification Series Part 1: SystemVerilog Fundamentals - Udemy
- Verilog HDL: VLSI Hardware Design Comprehensive Masterclass - Udemy
Projects
- Priority Arbiter-Based Resource Arbitration Controller with Safe Clock Domain Crossing, 2026-01-01, 2026-02-01, Designed a multi-clock traffic controller RTL in SystemVerilog with asynchronous-to-synchronous reset synchronization, 2 flip-flop CDC synchronizers for request crossing, configurable park control register, and priority-based grant logic; performed static signoff using Synopsys SuperLint to ensure CDC and lint-clean design., https://github.com/koushikmt660-hub/Resource-Controller
- Formal Property Verification of ULT IP Blocks (SVA-Based), 2025-10-01, 2026-01-01, Performed Formal Property Verification (FPV) of ULT IP blocks using Assertion-Based Verification (ABV) in Cadence JasperGold to validate functional correctness and protocol compliance.
- Functional Verification of UART using SystemVerilog, 2026-05-01, 2026-05-01, Developed a SystemVerilog-based self-checking verification environment for the UART protocol, including generator, driver, monitor, scoreboard, and assertions (SVA) to verify transmission, reception, parity, and framing functionality.
- Design and Analysis of a Multiplexer-Based Low-Power Full Adder, 2024-09-01, 2024-12-01, Designed and simulated a high-speed, low-power full adder using multiplexer-based pass transistor logic (PTL) with full-swing outputs, achieving improved power-delay performance suitable for VLSI arithmetic units.
Timeline
Graduate Technical Intern
Intel
06.2025 - 05.2026
M.E. - Microelectronics and VLSI Technology
MSIS MAHE
B.E. - Electronics and Communication Engineering
JNNCE VTU