Koyel Das

Project - PCIe DL Layer

• Data Link Layer Protocol Implementation: Developed and implemented PCIe Data Link Layer (DLL) protocol, including transaction layer packet (TLP) framing, CRC generation, and error detection/correction mechanisms to ensure reliable communication between PCIe devices.
• Link Initialization and Error Handling: Expertise in the design and verification of link training and initialization procedures, handling link status, and implementing robust error handling techniques such as retransmission protocols and error recovery (e.g., Data Link Layer Retry).
• Flow Control and Buffer Management: Designed and optimized flow control mechanisms within the Data Link Layer to ensure efficient packet delivery and prevent buffer overflows, managing the insertion of flow control credits.

Project - KaanapaliT_1.0, Balsam_1.0, Nords_1.0, HawiT_1.0, Camano, Monaco.

Responsibilities:

• RTL Quality Assurance: Led RTLQA and UFLOW runs for common cores, ensuring design quality through rigorous Lint and CDC checks and adhering to release checklists for robust design validation.
• Tool Validation and Debug Support: Validated the BLAnalyzer tool, providing debug support to users and resolving JIRA issues to ensure smooth tool functionality and accurate design analysis.
• LEC Script Validation: Validated LEC scripts on DL4 cores, offering technical support for debugging and ensuring compatibility with design requirements.
• SEC & LEC Execution: Ran SEC (Structural Equivalence Checking) and LEC (Logical Equivalence Checking) tools, analyzing reports to identify and resolve design inconsistencies.
• End-to-End RTL Verification and LINT/CDC Analysis: Executed and debugged RTL simulations and Lint and CDC checks at both block and top levels using VCS and Spyglass, ensuring design accuracy and constraint alignment through targeted updates and waivers.

Responsibilities:

• RTL Design and Integration: Hands-on experience in RTL design, RTLQA checks, LINT/CDC, UFLOW, integration, and synthesis across multiple IP development projects, with expertise in tools like VCS, Spyglass, and Synopsys Design Compiler.
• Timing and Synthesis Expertise: Strong knowledge in ASIC and FPGA logic synthesis, timing analysis, and achieving timing closure, ensuring high-performance designs across various platforms.
• Bus Architecture and Power Optimization: Familiar with APB, AHB, and AXI bus architectures, with a foundational understanding of low-power concepts (UPF) and extensive experience in Linux-based environments for design and debugging.

Project - Gigabit Ethernet MAC

• High-Speed Data Transfer: Enables full-duplex communication at 1 Gbps, ensuring efficient data transmission for high-bandwidth applications in networking systems.
• MAC Layer Functionality: Implements essential data link layer tasks such as frame encapsulation/decapsulation, address filtering, CRC error checking, flow control and controlling data flow (pause frames).
• Integration Ready: Commonly integrated into SoCs and FPGAs, offering flexible interfacing with physical layer devices (PHYs) via standard interfaces like GMII or RGMII.