Quartus Prime
KUMAR RISHAV
Design Verification Engineer
Bengaluru
" The moment you think of giving up, think of the reason why you held on so long. "
Summary
Reliable, resourceful and an adept multi-tasker who thrives in a high pressure work environment. Passionate about staying updated with emerging trends in the industry and committed to continuous learning and professional growth. Excellent problem-solving, analytical, and communication abilities, complemented by a collaborative and detail-oriented approach. Proactive, and committed to delivering accurate and efficient verification solutions to ensure the functionality and reliability of digital designs.
Overview
2
2
Years of Professional Experience
1
1
Certification
Skills
- Verilog HDL
- System Verilog
- Assertion Based Verification - SVA
- Universal Verification Methodology (UVM)
- Coverage Driven Constraint Random Verification
- Functional coverage
- Static Timing Analysis (STA)
- EDA Tools- Quartus Prime, ModelSim, QuestaSim, Xilinx-ISE
- Object Oriented Programming (OOP)
- Scripting Languages- Python, Perl
- Programming Languages- C, C
Work History
Software Development Associate
LitSpark Solutions
05.2022 - Current
- Collaborated with cross-functional teams to analyze software requirements and design solutions.
- Proficient in programming languages such as C++ and Python. Participated in code reviews to enhance code quality and identify potential improvements.
- Conducted thorough testing, debugging, and troubleshooting to ensure robust and error-free program.
- Resolved complex technical issues and challenges to ensure timely project delivery.
- Proficient in using version control systems (e.g., Git) to manage source code and track changes.
Education
Bachelor of Technology - Electrical & Electronics Engineering
11.2017
- 6.4 CGPA
- Vocational Training, NTPC- Farakka, 2016
- Vice President of Vivaann(NGO)
Higher Secondary -
2013
- Percentage- 73.2 %
Secondary -
2011
- 9.4 CGPA
Certification
- Advanced VLSI Design and Verification Course, Maven Silicon- Bengaluru [ Feb 2024- Present ]
Projects
- AHB to APB Bridge IP Core Verification
HVL: System Verilog
TB Methodology: UVM
EDA Tool: QuestaSim
Description: AHB-to-APB Bridge is an interface bus system to build data flow synchronization between high-speed AHB and low- performance APB IPs, based on AMBA protocols.
- Router 1X3-RTL Design and Verification
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools: QuestaSim and Quartus Prime
Description: Transferring data from source to destination. This system works on a 3-layer network protocol of the TCP/IP Model.
Components designed: FSM, Synchronizer, Register, Three FIFOs.
Software
QuestaSim
ModelSim
Xilinx ISE
Timeline
Software Development Associate - LitSpark Solutions
05.2022 - Current
GITAM University - Bachelor of Technology, Electrical & Electronics Engineering
KCP Siddhartha Adarsha Residential Public School - Higher Secondary,
KCP Siddhartha Adarsha Residential Public School - Secondary,
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