Summary
Overview
Work History
Education
Skills
Accomplishments
Websites
Timeline
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Krishnapal Singh

Krishnapal Singh

Hyderabad

Summary

Highly skilled Senior Verification Engineer with proven experience in ASIC design verification methodologies. Specialized in C/C++, System Verilog, and UVM. Successfully led teams to deliver complex technical projects on time while maintaining high quality standards.

Overview

13
13
years of professional experience

Work History

Senior Verification Engineer

NVIDIA
Westford
12.2022 - 02.2024
  • Worked on the Run-time In-system testing (RIST) safety features targeting automotive products.
  • My responsibilities involved working on low-power and interrupt sub-feature verification and corresponding code coverage analysis for RIST.
  • Tests were written using the C framework, testplan developed in python. Low-power feature checkers provided by the corresponding unit verification team were integrated into the sub-system-level testbench.

Senior Verification Engineer

NVIDIA
Hyderabad
06.2020 - 10.2022
  • Verification lead for ARM Cortex-A9 MPCORE processor-based audio subsystem, handling a team of 8 members.
  • Team owned - Unit and SOC verification, FPGA validation, C-MODEL validation for early S/W bring-up, and Unit perf validation.
  • Created a UVM testbench (TB) from scratch for functional verification and a hybrid SystemC/SystemVerilog TB for unit performance validation.
  • Successfully led the FPGA and Silicon bring-up for the Audio sub-system features.

Senior Verification Engineer

NVIDIA
Hyderabad
10.2018 - 05.2020
  • Wrote architectural model (a-model) in C/C++ from scratch for DSI protocol layer for unified DPHY and CPHY protocol layer implementation.
  • Led the DSI CPHY IP verification for the in-house design owning the unit verification.
  • Created a UVM TB from scratch for the DSI CPHY IP, developed scoreboard, and additional required protocol timing/checkers.. The receiver side VIP used was an external VIP from Synopsys.

Senior Verification Engineer

NVIDIA
Hyderabad
05.2014 - 10.2018
  • Worked on first generation of sensor and boot processor based sub-system based verification for the Tegra product line at NVIDIA.
  • Co-owned the boot code development, Cortex-R5 processor and related units (Address space translation, Network-onchip interconnect) integration verification.
  • Driven significant verification methodology improvements with a team of 5 members for Sensor and Boot Processor subsystem verification during the 2nd generation.
  • Adopted Formal property verification (FPV) for hardware synchronization primitives IP and wrote multiple unit TBs from scratch for Address space translation, Hardware Safety Manager, TCM IPs.

Verification Engineer

NVIDIA
Hyderabad
08.2011 - 04.2014
  • Joined as new college graduate (NCG) in the multimedia architecture and verification group at NVIDIA.
  • Worked on CMODEL development using C/C++ framework and verification of Digital microphone, Speaker controller and Mixer IPs.
  • Silicon validation lead for Audio IP.

Education

Bachelor of Technology - Electronics And Communications Engineering

International Institute of Information Technology
Hyderabad
05-2011

Skills

  • C/C
  • System Verilog
  • UVM
  • ARM processor verification
  • Debugging
  • Team management

Accomplishments

Publications:

  • Mode-switch: Flexible Sequence Creation Methodology for Verifying a Highly Configurable DSI IP | SNUG Silicon Valley, 2020
  • IP-XACT (IEEE-1685 standard) Based Approach to Automate IP-Freeze | SNUG Silicon Valley, 2020
  • Adaptive UVM <-> AMOD Testbench for Configurable DSI IP | DVCON INDIA, 2019
  • Text-dependent speaker identification using combined evidences from source and system feature, ICON , 2010

Academics

  • Featured in Dean's list of Academic Excellence for Spring 2009, Monsoon 2009 and Monsoon 2010 . Rank 3 holder in the ECE (Electronics and Communications) branch.
  • Top position in Secondary School Examination: Awarded for excellence for securing Top position in school in Secondary school Examination.

Websites

Timeline

Senior Verification Engineer

NVIDIA
12.2022 - 02.2024

Senior Verification Engineer

NVIDIA
06.2020 - 10.2022

Senior Verification Engineer

NVIDIA
10.2018 - 05.2020

Senior Verification Engineer

NVIDIA
05.2014 - 10.2018

Verification Engineer

NVIDIA
08.2011 - 04.2014

Bachelor of Technology - Electronics And Communications Engineering

International Institute of Information Technology

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Krishnapal Singh