Krushna Chavan

An independent and self-motivated graduate to achieve a responsible position and personal goals by exploring myself more efficiently in an industry with full determination and expand my knowledge by working hard and learning new technologies

• President of Music Club at VPKBIET Baramati
• First Rank in Music Podcast at College level
• Smart India Hackathon(SIH) Participation

Vidya Pratishthan's Kamalnayan Bajaj Institute of Engineering and Technology, 2020, 2024

• Certificate Of Completion Of Python 3.4.3 Training Conducted By IIT BOMBAY, 12/01/21, 12/01/21
• Completion Certificates Of Matlab On Mathswork, 12/01/22, 12/01/22
• Python Programming By Edusera, 10/01/22, 11/01/22
• Machine Learning And Linear Regression certificate By Leaps Analytica, 08/01/22, 09/01/22
• IBM Skill Build Edunet Foundation, 08/01/22, 10/01/22
• The Spark Foundation, 08/01/22, 09/01/22

• Marathi, Native or Bilingual Proficiency
• Hindi, Full Professional Proficiency
• English, Professional Working Proficiency

• Singing
• Cricket

• Breast Cancer Detection Using Machine Learning:Breast cancer is the most common reason for deaths due to cancer. It is very necessary to detect cancer at early stages. There are various Machine Learning techniques available for the purpose of diagnosis of breast cancer data. Making a web application that can analyze tumor reports and predict whether patient is suffering from cancer or not. Our web application is user friendly and having accuracy almost more than 95%.We have used 4 Machine Learning algorithms while implementing and one with maximum accuracy is used in final output thus maximizing the project accuracy.
• Remote Data Monitoring System for Greenhouse (IOT):The main objective of this project is to increase output by utilizing new technology to enhance current farming practices.The main aim of the project is to manage and control the greenhouse system
• Designing and Development of a UART protocol using Verilog and a UVM testbench(VLSI):The main objective of this project is to design and verify a full duplex UART module using System Verilog (SV). It is a serial communication protocol which provides communication between the systems without using clock signal. It converts parallel data into serial format and transmits the same.

• First Rank in Music competition