K S AKSHAY KAUSHIK
BENGALURU
Summary
Highly-motivated employee with desire to take on new challenges. Strong worth ethic, adaptability and exceptional interpersonal skills. Adept at working effectively unsupervised and quickly mastering new skills.
Overview
3
3
years of professional experience
Work History
Component Design Engineer
Intel Corporation
BENGALURU
08.2021 - Current
- Conducted comprehensive quality checks on Physical Design Verification runsets, ensuring adherence to design specifications and standards.
- Expertly debugged DRC rule deck failures during regression testing, meticulously documenting issues for review by the development team.
- Worked on Intel16E,Intel3-T,Intel3-E technologies.
- Developed and implemented layout patterns based on the Redbook design manual to verify compliance with design rules, enhancing the effectiveness of the QA regression suite.
- Automated the central regression system, significantly improving efficiency and reducing manual effort in testing processes.
- Managed and maintained the test bench infrastructure, ensuring its reliability and functionality.
- Executed physical verification runsets utilizing Synopsys ICV, Siemens Calibre, and Cadence Pegasus tools on Intel database, emulating virtual tape-in scenarios.
- Identified and triaged discrepancies between multiple runsets, providing clear and actionable insights for review and resolution.
Education
MTech in VLSI Design (CGPA 8.77)
Vellore Institute of Technology
Vellore,Tamil Nadu01-2022
B.E in Telecommunication (CGPA 8.54)
RVCE
Bangalore01-2018
Karnataka Pre-University Board, Class 12th Examination (Percentage - 87%) -
Deeksha Centre For Learning PU College
Bangalore01-2014
CBSE Board, Class 10th(CGPA 9.4) -
JSS Public School
Bangalore01-2012
Skills
- CalibreDRV & Cadence virtuoso: Skilled in utilizing these tools for DRC verification
- TCL
- Python
- Verilog
- STA
Accomplishments
- GATE Qualified Student: Successfully passed the Graduate Aptitude Test in Engineering (GATE) .This accomplishment reflects strong academic aptitude and dedication to continuous learning and professional development.
- Recognized for Enhancements in Automation: Acknowledged for significant contributions in improving scripts and automation processes, resulting in increased efficiency and productivity within the team.
- Department Award: Awarded for outstanding contributions to the successful delivery of Intel3-T and Intel3-E projects, demonstrating dedication and excellence in project execution
Affiliations
- Class Representative ,VIT University (during Mtech) :- Facilitated communication between faculty and students, addressing concerns ,disseminating important information ensuring productive discussions and resolution of issues.
- Event Organizer,Intel Corporation :- Collaborated with a team to plan, organize, and execute various events within Intel Corporation .
- Team Support and Celebration Coordinator,Intel Corporation:- Actively contributed towards solving Technical/Non technical problems within the team.Played a key role in fostering a positive team culture by organizing and participating in celebrations for important occasions, such as project milestones and individual birthday celebrations
Projects
MTech Project :
1. Design of 64 bit ALU using Vedic mathematics
The designed ALU comprised of four units adder,subtractor,multiplier and divider which were designed using verilog programming language on modelsim and was synthesized on Intel Quartus Prime.
2. Threshold Voltage variability in MOSFETs and FINFETs: MOSFET and FINFET structure was created using TCAD and the threshold voltage variations were examined based on the factors that include work function, doping concentration, oxide thickness and trapped charges.
3. Bluetooth controlled robot using Arduino & mobile phone [B.E.]
Mobile transmits command using its in-built Bluetooth to the robot which has bluetooth module for controlling movements.
Timeline
Component Design Engineer
Intel Corporation
08.2021 - Current
MTech in VLSI Design (CGPA 8.77)
Vellore Institute of Technology
B.E in Telecommunication (CGPA 8.54)
RVCE
Karnataka Pre-University Board, Class 12th Examination (Percentage - 87%) -
Deeksha Centre For Learning PU College
CBSE Board, Class 10th(CGPA 9.4) -
JSS Public School
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