Summary
Overview
Work History
Education
Skills
Projects
Accomplishments
Activities
Certification
Timeline
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K S Akshay Kaushik

BENGALURU

Summary

Driven Component Design Engineer with a proven track record at Intel Corporation, enhancing design quality and efficiency through expert use of CalibreDRV and Python. Spearheaded the automation of Runset QA flow, significantly boosting productivity. Known for meticulous debugging skills and a knack for innovative problem-solving, blending technical prowess with collaborative teamwork.

Overview

3
3
years of professional experience
1
1
Certification

Work History

Component Design Engineer

Intel Corporation
BENGALURU
08.2021 - 05.2024

31/08/2021 – 27/05/2022 (Intern)

06/06/2022 –17/05/2024 (Full time)

  • Conducted comprehensive quality checks on DRC runsets to ensure design specification adherence as a part of Process Design Kits (PDK) Runset QA team.
  • Expertly debugged DRC rule deck failures during regression testing, meticulously documenting issues for review by the development team
  • Worked on Intel16E, Intel3-T, Intel3-E technologies
  • Developed and implemented layout patterns based on the Redbook design manual to verify compliance with design rules, enhancing the effectiveness of the QA regression suite
  • Automated the Runset QA flow, significantly improving efficiency and reducing manual effort in testing processes
  • Executed physical verification runsets utilizing Synopsys ICV, Siemens Calibre, and Cadence Pegasus tools on Intel database, emulating virtual tape-in scenarios
  • Identified and triaged discrepancies between multiple runsets, providing clear and actionable insights for review and resolution
  • Intern from 31/08/2021 to 27/05/2022
  • Full time from 06/06/2022 to 17/05/2024

Education

MTech - VLSI Design

Vellore Institute of Technology
Vellore, Tamil Nadu
05-2022

B.E - Telecommunication

RVCE
Bangalore
01.2018

Karnataka Pre-University Board, Class 12th -

Deeksha Centre For Learning PU College
Bangalore
01.2014

CBSE Board, Class 10th -

JSS Public School
Bangalore
01.2012

Skills

  • CalibreDRV
  • Cadence virtuoso
  • TCL
  • Python
  • Verilog
  • STA

Projects

M.Tech Project:

1. Design      of 64-bit ALU using Vedic Mathematics

  • Designed an ALU with adder, subtractor, multiplier, and divider units using Verilog.
  • Simulated using ModelSim and synthesized on Intel Quartus Prime for system integration.

2. Threshold      Voltage Variability in MOSFETs and FINFETs

  • Utilized TCAD to design MOSFET and FINFET structures and analyzed threshold voltage variations.
  • Investigated the impact of work function, doping concentration, oxide thickness, and trapped charges.

B.E. Project:

1. Bluetooth-Controlled Robot using Arduino & Mobile Phone

  • Integrated a Bluetooth module with an Arduino-based robot for remote control using a mobile device.

Accomplishments

  • GATE Qualified Student: Successfully passed the Graduate Aptitude Test in Engineering (GATE). This accomplishment reflects strong academic aptitude and dedication to continuous learning and professional development.
  • Recognized for Enhancements in Automation: Acknowledged for significant contributions in improving scripts and automation processes, resulting in increased efficiency and productivity within the team.
  • Department Award: Awarded for outstanding contributions to the successful delivery of Intel3-T and Intel3-E projects, demonstrating dedication and excellence in project execution.

Activities

  • Class Representative, VIT University (Mtech), Facilitated communication between faculty and students, addressing concerns, disseminating important information ensuring productive discussions and resolution of issues.
  • Event Organizer, Intel Corporation, Collaborated with a team to plan, organize, and execute various events within Intel Corporation.
  • Team Support and Celebration Coordinator, Intel Corporation, Actively contributed towards solving Technical/Non-technical problems within the team. Played a key role in fostering a positive team culture by organizing and participating in celebrations for important occasions, such as project milestones and individual birthday celebrations.

Certification

  • Physical Design and SoC Verification Training – Maven Silicon, Bangalore (Currently Undergoing)

Timeline

Component Design Engineer

Intel Corporation
08.2021 - 05.2024

MTech - VLSI Design

Vellore Institute of Technology

B.E - Telecommunication

RVCE

Karnataka Pre-University Board, Class 12th -

Deeksha Centre For Learning PU College

CBSE Board, Class 10th -

JSS Public School

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K S Akshay Kaushik