Summary
Overview
Work History
Education
Skills
Languages
Timeline
Generic

Lakshmi Dandu

Bangalore

Summary

Flexible hard worker ready to learn and contribute to team success.

To pursue a challenging career and be part of a progressive organization that gives scope to utilize my skills and abilities in latest technologies and to enhance my knowledge, skills with dedication and hard work. Diligent Engineer takes responsibility for ongoing projects and new endeavor planning. Provides deep technical knowledge and common-sense business acumen for initiatives. Committed to reaching business goals through technical management and impactful analyses.

Overview

5
5

Years of professional Experience

Work History

TFM Engineer

TechMahindra
Bangalore
08.2022 - 06.2023
  • Hands on experience on EDA tools like Lint,CDC,Synthesis, LEC
  • Applied technical knowledge to help promote safe work environment and enhance customer satisfaction.
  • Identified and implemented most acceptable resolutions to complex engineering problems.
  • Analyzed and interpreted complex electrical and mechanical systems.
  • Provided feedback to design engineers on customer problems or needs.
  • Developed preventive maintenance programs and supported energy conservation improvements.
  • Integrating the RTL codes on SOC using Collage tool
  • Workedo n all the tools and did all the setup for SS
  • Worked in lint,cdc, H2b(Trail synth)
  • Worked on H2b ,file generation, Vcs Elab and debugged the errors
  • Running the tools and debugging the errors lint,cdc,synth

Senior Engineer

UST Global
Bangalore
02.2021 - 07.2022
  • Roles and Responsibillity:
  • Performed root cause analysis of problems, documented faults in tracking system and generated daily reports.
  • Integration Activities
  • CDC -Worked for both IP and SOC Enabling goals and checking and debugging the errors
  • Running CDC on IP and SOC and debugging errors
  • Worked on PLDRC(Lint) and debugged the errors.
  • Performed root cause analysis of problems, documented faults in tracking system and generated daily reports.
  • Analyzed design or requirement information for equipment or systems.
  • Communicated with clients and coworkers about analysis results.

VLSI RTL Design Engineer

02.2017 - 06.2020

11.2016 - 02.2018
  • Verdi, Spyglass tools and Linux OS
  • Roles and Responsibility:
  • Evaluated existing RTL design based on latest available specification
  • Worked on the RTL of the new features that are to be included in the new generations of the custom channel
  • And Checked the quality of RTL code using Lint and CDC
  • Synthesized the RTL design using Design Compiler
  • Worked on equivalence checking automation Used Formality for the checks
  • Memory Serial Interface IP v0,v1.

10.2016 - 04.2017
  • Model sim, Lint, CDC and Linux
  • Roles and Responsibility:
  • Worked in an ASIC design flow team developing and design RTL code
  • Designed and implemented RTL code in Verilog and schematics
  • Debugged RTL which was written in Verilog to identify the faulty before reporting a defect
  • Developed RTL design, constraint development, logic synthesis DC, and timing analysis/debug
  • Quality checked RTL Code using Lint and CDC spyglass tools and Debugged the violations
  • Synthesized the modified RTL code on spyglass tool and debugging and fixing constraints – power ,timing and area and implement the netlist.

Education

B-Tech - Electronics & Communication Engineering

Anna University
01.2015

Skills

  • TECHNICAL SKILLS:
  • Summary : ASIC Design flow, RTL Frontend
  • Tools : Model Sim, Spyglass-Lint, CDC, Synthesis, LEC
  • Languages : Verilog
  • Documentation Software: Microsoft Word, Microsoft Excel, Microsoft Power Point
  • OS platforms : Windows, Linux
  • SKILLS AND OTHER ACTIVITIES
  • Good interpersonal communication skills
  • Good Grasping power and passionate to learn new technologies
  • Confidence, Time management and Hard-working
  • Project management and planning

Languages

  • English, Telugue

    • Timeline

    TFM Engineer

    TechMahindra
    08.2022 - 06.2023

    Senior Engineer

    UST Global
    02.2021 - 07.2022

    VLSI RTL Design Engineer

    02.2017 - 06.2020

    11.2016 - 02.2018

    10.2016 - 04.2017

    B-Tech - Electronics & Communication Engineering

    Anna University

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