Summary
Overview
Work History
Education
Skills
Affiliations
Accomplishments
Certification
Languages
Timeline
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Lakshmi Narasimha Reddy Gunta

Hyderabad

Summary

Overall 8 years of experience in physical design with a track record of 6 successful tapeouts across 5nm, 10nm, 16nm, and 28nm process nodes. Expertise in flow setup for synthesis and place-and-route (PNR), utilizing EDA tools such as DC, DCT, Innovus and ICC2. Demonstrated ability to enhance system efficiency and reduce project costs through innovative engineering solutions and adherence to best practices. Dynamic senior engineer with a strong focus on timing closure and problem-solving in high-stakes environments.

Overview

8
8
years of professional experience
1
1
Certification

Work History

Senior Engineer 2

Ceremorphic technologies
Hyderabad
12.2023 - Current
  • Developed innovative solutions to enhance system efficiency and reduce project costs.
  • Flow bring-up to synthesis and PNR.
  • Implemented best practices in engineering standards and procedures.
  • Surveyed sites, collected measurements, and assessed project conditions.
  • Worked for Chiptop on a 16nm test chip, which has 10 blocks.
  • Handled 2 blocks.
  • Created chip floorplan based on synthesis area. - 9.5 mm²
  • Fixed the DRCS at chip top.
  • Qslinks -3, LPDDR6, NP3, PLL, and digital top blocks are part of the chip.
  • Worked for digital top and QSLink blocks from netlist to GDS2.
  • Integration of all closure blocks into the chip top, and closed at all aspects (timing, DRC, LVS, ANT).

Senior Engineer

Quest global
Hyderabad
12.2021 - 09.2023
  • Worked for Nvida client 5nm Technode
  • Handled block from synthesis to gds2.
  • Created bounds in synthesis to resolve the timing issues on IO paths.
  • Fixed reset tree build issues in placement stage and created guides for modules to optimize the timing.
  • Cts Trials- useful skew and created clock skew groups.
  • Fixed the PNR drcs
  • DRC, LVS, ANT.

Physical Design Engineer

Wipro
Hyderabad
02.2021 - 12.2021
  • Executed Intel ADPN-B0 eco project, generating functional ecos, and implementing on routed DB.
  • Timing closure, Calibre LVS DRC ANT
  • With the support of Intel team, got feedback on redhawk IR issues, Got the locations from the team, fixed it on metal Eco stage.

Engineer

Altran Technologies India Pvt Ltd
Coimbatore
02.2019 - 01.2021
  • Served as a buffer in INTEL CHG-TGLGT-1 project, ensuring synthesis and timing closure at block level.
  • Executed ECO implementations and achieved timing closure for both INTEL 10nm projects.
  • Developed Eco file and distributed to block owners for integration.
  • Utilized RDT flow to complete synthesis through place and route processes.
  • Conducted trials on CTS by adjusting DOPs to meet skew and latency targets.
  • Ensured DRC compliance during route optimization stage using ICC2 tool.
  • Achieved subsystem level timing closure for INTEL 10nm+++ SPRD-B0 project.
  • Collaborated with teams to streamline project workflows and enhance output.

Engineer

Avast Technologies Pvt Ltd.
Hyderabad
08.2017 - 09.2018
  • In-House Project (Intel-16nm)
  • Executed block-level PNR workflows to enhance design efficiency.
  • Developed a floor plan accommodating 80 macros with an instance count of 1.2 million.
  • Optimized placement through path grouping and bound trials.
  • Conducted clock building and balancing to ensure timing accuracy.
  • Performed routing of the design and resolved all DRC violations in ICC tool.

Education

Bachelor of Science - Electrical, Electronics And Communications Engineering

Lovely Professional University
Punjab
05-2017

High School Diploma -

Narayana Junior College
VijayaWada
03-2013

High School Diploma -

Oxford Residential School
Dachepalli
03-2011

Skills

  • EDA tools: Innovus, ICC2, PT, DC, DC-T, Calibre
  • Floorplan optimization
  • Synthesis and place-and-route
  • Design rule checking and layout versus schematic, Antenna Checks

Affiliations

  • Playing Cricket & I am the captain to lead my team be in winning side, EOD the team spirit gives happiness even if We lose.

Accomplishments

  • Inter-School Competition winners Team in Cricket.
  • Recognition in the project's closure.

Certification

  • Hier and Block Implementation Course in Cadence Innovus

Languages

Telugu
First Language
English
Proficient (C2)
C2
Hindi
Proficient (C2)
C2

Timeline

Senior Engineer 2

Ceremorphic technologies
12.2023 - Current

Senior Engineer

Quest global
12.2021 - 09.2023

Physical Design Engineer

Wipro
02.2021 - 12.2021

Engineer

Altran Technologies India Pvt Ltd
02.2019 - 01.2021

Engineer

Avast Technologies Pvt Ltd.
08.2017 - 09.2018

Bachelor of Science - Electrical, Electronics And Communications Engineering

Lovely Professional University

High School Diploma -

Narayana Junior College

High School Diploma -

Oxford Residential School

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Lakshmi Narasimha Reddy Gunta