Lohith R
Bengaluru
Summary
With a proven track record at Aryavarta circuits Pvt Ltd, I excel in analog mixed signal circuit design and high-speed interface development. My expertise in simulation and characterization of analog blocks, combined with strong analytical skills, has significantly enhanced product performance. Experience working with the SOC team for their requirement. Renowned for developing innovative solutions and a keen eye for detail, I consistently deliver exceptional results.
Overview
1
1
year of professional experience
Work History
GPIO1p01p2 I/O
INTEL PVT LTD
06.2024 - Current
- Design and Verifications of GPIO TX & RX with core supply voltage is 0.55V to 0.825V & IO supply voltage is 0.95 to 1.05V for 1p0 mode and 1.14V to 1.26V for 1p2 mode, F= 200MHz & load cap is 10pF
- Adding the proper spf/simulation file (layout spf) to all test cases & giving the input stimulus
- Aging: gradual aging simulations are performed to check the waveform with fresh, aged, and stress condition also measure Delta temp, idsat, and dvt for a given spec
- EOS: stress simulation is performed measure the violations like db, sb, gd, ds
- EMIR: for a given spf we run FSDB file generation, TOTEM flow & check the REPORT (IR drop & RV violations, max LTE violation ext)
- All the measurements are taken care, fire across the corner & results are documented
- Done ac, dc and transient analysis & monte carlo + aging simulation
GPIO 1P8 I/O
INTEL PVT LTD
11.2023 - Current
- Design and Verifications of GPIO TX with core supply voltage is 0.54V to 1.1V & IO supply voltage is 1.71V to 1.89V, F= 100MHz & load cap is 10pF
- Circuit design of Driver Level Shifter
- Experience working with the SOC team for their requirements in the platform.
12-bit, 80-MSPS Pipelined ADC
Sabertek Inc
- The architecture consists of Three MDAC stages followed by 4 Bit Flash ADC
- Open Loop Signal Buffer is used to isolate Filter and ADC Module
- Gm-R Stage followed by Gain Boosting OTA stage used to improve UGB and Open Loop Gain to reduce the current consumption
- Internal voltage reference block implemented
- Class AB OTA, 3.5 Bit MDAC Design, Integration and Top Level Simulations
PLL (Verification)
Skyechip (Malaysia)
- Reference clock frequency 50MHz to 300MHz Long-term jitter 5ps at 100MHz reference clock @ 3.2GHz VCO clock, Deterministic Jitter<5ps Random Jitter (rms) <800fs
- Majorly worked on PFD and charge pump and checked all the corners pvt simulations of block level and top level of PLL in top level
- The vctrl voltage and VCO Output frequency at locking time was checked the peak to peak Periodic jitter & rms jitter of the PLL
Strong Arm Latch Comparator
US Client
- Strong Arm Latch Comparator has been designed for 12-Bit 10MSPS Pipeline ADC
- Propagation Delay 500ps, Offset voltage <15mV, Current consumption 28uA
- Circuit design and verification of Comparator
Fully Integrated Voltage Regulators (FIVR)
INTEL PVT LTD
- Worked on BGR (Bandgap voltage references) block
- Verification flows conducted: All Reliability flows which includes RV (Reliability Verification), HV (High Voltage DRC), Aging, Aging with Tmap, EOS (Electrical Over Stress), ELF (Early Life Failure)
- Familiarity on Siliconsmart and Dynamic Leakage Check flows
Education
B. E. - Electronics and Instrumentation
VTU
Skills
- Analog Mixed Signal Circuit Design
- High-Speed Interface
- Data converters
- Analog Mixed signal circuit design of Two stage OTA
- Comparator
- SAL
- Schmitt Trigger
- Pipeline ADC
- Simulation & characterization of different analog blocks
- Developing test benches
- MOS transistor characteristics
- Analog engineering techniques
- Analysis & approaches
- Analog & Digital circuits
Timeline
GPIO1p01p2 I/O
INTEL PVT LTD
06.2024 - Current
GPIO 1P8 I/O
INTEL PVT LTD
11.2023 - Current
12-bit, 80-MSPS Pipelined ADC
Sabertek Inc
PLL (Verification)
Skyechip (Malaysia)
Strong Arm Latch Comparator
US Client
Fully Integrated Voltage Regulators (FIVR)
INTEL PVT LTD
B. E. - Electronics and Instrumentation
VTU
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