Lokathilak Gowda
Bengaluru,Karnataka
Summary
Detail-oriented and results-driven VLSI Design Verification Engineer with 5+ years of experience at Wipro, specializing in SystemVerilog, UVM, and complex SoC/block-level verification. Proven success in leading verification activities, converting native testbenches to UVM, automating workflows, and collaborating with architects/RTL teams to deliver high-quality silicon-proven designs. Recognized for strong debugging, ownership, and mentoring abilities. Adept at building robust verification environments that improve coverage, performance, and overall efficiency.
Overview
6
6
years of professional experience
Work History
Lead DV Engineer | Former Verification Engineer
Wipro
07.2019 - Current
- Led block-level and subsystem verification for multiple IPs, ensuring complete adherence to design specifications.
- Designed and implemented UVM-based verification environments , including monitors, checkers, and reusable sequences.
- Developed feature-based test plans, coverage plans, regression plans , and executed verification strategies from scratch.
- Drove coverage closure , analyzing functional/code/assertion gaps, and implementing tests or assertions to achieve 100% targeted metrics.
- Strong debugging ownership: provided deep insights on RTL issues, waveform analysis, protocol violations, and simulation mismatches.
- Played a key role in scenario based test development , collaborating with clients to understand specifications and validation requirements.
- Provided critical feedback on new RTL drops , identifying corner-case issues early in the cycle.
- Developed automation utilities using Python/Shell to speed up regression execution, logfile parsing, and coverage extraction.
- Conducted reviews of testcases, sequences, and UVM components to maintain coding discipline and UVM best practices.
- Mentored new team members, providing KT on UVM flow, environment architecture, debugging, and design understanding.
- Recognized for proactive collaboration with architects, designers, and cross-functional teams to ensure faster resolution of blockers.
Education
Bachelor of Engineering - Electronics And Communications Engineering
RV College of Engineering
Bengaluru, India01-2019
Skills
- SystemVerilog, UVM, SVA, Testbench Architecture
- Functional Verification & Constrained-Random Testing
- Debugging Tools: Verdi
- Simulators: VCS, Questa, Xcelium
- AMBA Protocols (AXI/AHB/APB), SoC Block-Level DV
- Python, Perl Scripting for Automation
- Verification Planning, Estimation & Ownership
- Regression Management & Analysis
- Mentoring Juniors & Code Review
- Cross-functional Collaboration with RTL, Architects & Validation
- Issue Triage, Root-Cause Analysis & Quality Improvements
Timeline
Lead DV Engineer | Former Verification Engineer
Wipro
07.2019 - Current
Bachelor of Engineering - Electronics And Communications Engineering
RV College of Engineering