Lokesh Mahor

Accruing over 3 years of experience in managing Verification Environments as a Design Verification Engineer, expertise extends to hands-on utilization of hardware languages like Verilog/System Verilog, SVA, and Coverage metrics. Proficient in formulating Verification Plans and Test Plans, with practical involvement in generating and utilizing test benches for verification through the UVM Framework. Demonstrated adeptness in team management, encompassing task assignment. Involvement spans protocols including AHB, AXI4Stream, APB, and JTAG, contributing actively to the development of Assertion and Scoreboard Logic.

• Shining Star Award by Softnautics - A MosChip Company
• Spot Award at Softnautics for Active Contribution to Project

• Config Security Verification - Nov 2022 – Present

      - UVMF Testbench Generation based on existing Config IP and Security IP Environment 

      - Development of Verification Plan and Test plan.  

      - Integration of Existing python script into UVM environment for creation of Authenticated and  Encrypted data 

       - Developed Test cases to Verify Functionality and Protocols in IP. 

       - Debugged Testcase Failures and Raised JIRA’s for Issues in RTL. 

       - Creation of python script to combine regression results from different testlist 

       - Coverage Merging, UNR and Coverage Analysis for Closure 

• Configuration IP LEVEL VERIFICATION - AUG 2021 – Nov 2022

      - Lead Config IP Verification Team and Assign Responsibility -

      - Development of Verification Schedule, Test Plan and Verification Plan 

      - UVMF Testbench Generation including predeveloped SUB IP UVMF Environment and QVIP  

      - Use AXI4Stream, AHB, JTAG and XSPI QVIPs for Protocol Verification 

      - Developed Test cases to Verify Functionality and Protocols in IP. 

      - Predictor, Assertion and Functional Coverage Coding 

      - Debugged Testcase Failures and Raised JIRA’s for Issues in RTL. 

      -  Coverage Merging, UNR and Coverage Analysis for Closure 

• JTAG Verification - MARCH 2021 – AUG 2021 -

      - Development of Verification Schedule, Test Plan and Verification Plan 

      - UVMF Testbench Generation including QVIP and RAL Model -

      - Creation of BFM to Support Additional Features in JTAG 

      - Developed Test cases to Verify Functionality and Protocols in IP. 

      - Predictor, Assertion and Functional Coverage Coding 

      - Debugged Testcase Failures and Raised JIRA’s for Issues in RTL. 

      - UNR and Coverage Analysis for Closure 

• Oscillator Verification - JAN 2021 – MARCH 2021

      - Development of Verification Schedule, Test Plan and Verification Plan 

      - Development clock generation logic for TB • UVMF Testbench Generation 

      - Assertion Coding to Verify Stimulus generated by Oscillator 

      - Debugged Testcase Failures and Raised JIRA’s for Issues in RTL. 

      - UNR and Coverage Analysis for Closure 

• DPI-C Development for Co-Verification - JAN 2021 – MARCH 2021

      - Development of C functions to support Co-Verification. 

      - Dummy SV top creation to Import Developed C function in SV using DPI 

• Bluetooth IP Verification - JUNE 2020 - OCT 2020
• UART-IP CORE VERIFICATION - APRIL 2020 - JUNE 2020
• ROUTER 1X3 – RTL DESIGN AND VERIFICATION - DEC 2019 - APRIL 2020

• Graphical Designing
• Social Work