MADAPANA LOKESWAR
Senior Electronics Engineer
CHENNAI,TAMILNADU
Summary
Experienced Hardware Designer with expertise in Signal and Power Integrity Engineer for Automotive electronics solutions. Proficient in all stages of hardware development, from concept to production. Proficient in utilizing industry-standard simulation tools and methodologies to ensure robust signal integrity and power delivery across complex PCB designs. Adept at collaborating with cross-functional teams to meet project objectives and deadlines effectively. Looking to leverage technical expertise and problem-solving skills to contribute to innovative projects in High speed design boards and Systems.
Overview
9
9
years of professional experience
Work History
Senior Electronics Engineer
VALEO India Private Limited
2019.02 - Current
- Managed cross-functional team of 3, ranging from entry-level SIPI analyzer and collaborated with Hardware development, Testing, EMC and PCB Layout
- Lead the SIPI team for Cutting edge ECU in Automotive technology for Autonomous driving
- Signal integrity simulation for High speed design PCB Layout for Automotive applications using Cadence PowerSI, SystemSI & Broadband spice
- Power integrity simulation for PDN measurement and Capacitor reduction & Value optimization
- Involved in Capacitor reduction using PI simulation tool for $2.5 per board & overall $30M USD
- Technical training and Knowledge sharing programs for the new joiners and Interns; reduced onboarding time for new hires by 30%
- Led the transition for creation of new SIPI team for CDA entity practice by implementing an electronic process system and a faster, safer and more accurate SIPI team; reduced Design failures and testing error time by 30% and office overhead by 10%
- Board bring up and Validation of ADAS based UCAP ECU for Automotive applications
- Involved in ECU to reach into production, to achieve on time delivery for customer BMW
- Tested Camera modules and supported other automotive ECU boards in Testing.
Hardware Design Engineer
Data Patterns
2015.10 - 2019.01
- Board designer for 3U VPX Kintex Ultra-scale FPGA based ADC module which supports base band applications with ADCs & waveform generation DACs
- Board designer for double width ADC based FPGA Mezzanine Card (FMC) module as per the VITA57.1 standard
- Redesign and testing of IO Timing module with 6U VME based ARTIX-7 FPGA , Configuration flash 256MB, User flash 128MB, user SRAM 16MB
- System designer for 3U VPX-XMC carrier module with high speed aircraft data and video signal processing interfaces for Head Mount Display
- Developed for BAE Systems, UK
- Testing and Debugging of a 12-lane PCI Express Gen 2 Switch card with 9 PCI Express ports.
Education
Embedded systems Engineering -
Birla Institute of Technology and Science, Pilani
PILANI, RAJASTHANSkills
Digital Literacy
Timeline
Senior Electronics Engineer
VALEO India Private Limited
2019.02 - Current
Hardware Design Engineer
Data Patterns
2015.10 - 2019.01
Embedded systems Engineering -
Birla Institute of Technology and Science, Pilani
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