Summary
Overview
Work History
Education
Skills
Behavioral Skills
Disclaimer
Timeline
Generic

Madhavi Janwade

Physical Design Engineer
Belgaum

Summary

Highly motivated and ambitious professional with a passion for the Semiconductor Industry, specifically in Physical Design Engineering. Committed to making a significant impact and contributing to the success of any company. Demonstrating expertise, skills, and capabilities to align with the company's vision and become a valuable asset in Physical Design mastery.

Overview

4
4
years of professional experience
6
6
years of post-secondary education

Work History

Physical Design Applications Engineer

Siemens EDA
07.2022 - 12.2023
  • Engaged in Siemens EDA Place and Route Tool - APRISA development
  • Executed PNR flow on a 16nm node, aiming to minimize block timing and power with reduced DRC count
  • Proficient in IR and EM analysis, conducting analysis within the Aprisa tool
  • Familiar with Hierarchical design flow, involved in a 7nm in-house hierarchical design featuring 7 million instances
  • Proficient in Top-Level Partitioning, Budget Timing, Block Copying, and Top-Level PNR
  • Contributed to presales activities for Onsemi conductor and implemented PNR flow in Aprisa to meet timing and power targets
  • Faced the challenge of reducing total dynamic power by 10% while maintaining design timing and DRC requirements

VLSI design Trainee

Maven silicon PVT LTD
12.2023 - 10.2024
  • Employ Synopsys tools like Design Compiler (DC), Tanner, Fusion Compiler (FC), and PrimeTime (PT) for physical design tasks
  • Proficient in logic synthesis using DC and Fusion Compiler, with a thorough understanding of the entire APR flow from synthesis to routing
  • Proficient in verilog and python
  • Skilled in setting up and validating constraints, generating detailed reports, and performing signoff checks
  • Engaged in projects focusing on the synthesis and place-and-route (PNR) of RISC-V processor and ROUTER

ASIC Physical Design Trainee

Chipedge technologies PVT LTD
09.2021 - 04.2022
  • Demonstrates proficiency in the comprehensive APR process, encompassing Logical Synthesis and Signoff
  • Skilled in the effective utilization of Synopsys ICC2
  • Successfully executed three block-level Place and Route (PNR) projects using ICC2
  • Familiar with various tools including DC, Formality, ICC2, and PT

Business Analyst Intern

Centelon IT Solutions
03.2021 - 08.2021
  • Spearheaded the implementation of Leadsquared CRM system
  • Managed client accounts within the educational technology and real estate sectors, successfully setting up a CRM infrastructure to optimize sales operations
  • Obtained certification in Leadsquared CRM

Education

BE - ECE

VTU University
01.2017 - 01.2021

Senior Secondary - undefined

KLE COLLEGE OF SCIENCE
01.2015 - 01.2017

Skills

Streamlined Physical Design

Behavioral Skills

  • Adaptability
  • Excellent Communication
  • Problem Solving
  • Critical Thinking
  • Self-motivated
  • Great work ethics

Disclaimer

I hereby declare that the above information is true as per my consent.

Timeline

VLSI design Trainee

Maven silicon PVT LTD
12.2023 - 10.2024

Physical Design Applications Engineer

Siemens EDA
07.2022 - 12.2023

ASIC Physical Design Trainee

Chipedge technologies PVT LTD
09.2021 - 04.2022

Business Analyst Intern

Centelon IT Solutions
03.2021 - 08.2021

BE - ECE

VTU University
01.2017 - 01.2021

Senior Secondary - undefined

KLE COLLEGE OF SCIENCE
01.2015 - 01.2017
Madhavi JanwadePhysical Design Engineer