Madhu Anandam

- Planned verification of complex Security hardware IPs at IP and subsystem level by understanding design specifications and interacting with Architecture and Design Engineers.

- Created and enhanced verification environments using System Verilog and UVM.

- Identified and wrote all types of coverage measures for stimulus.

- Debugged tests with design engineers to deliver design blocks.

- Closed coverage measures to identify verification holes and show progress towards tape-out.

- Collaborated with Software, Silicon Validation, and Silicon bring-up teams.

- Verified IP or digital systems including CPU, Direct Memory Access, interconnects, Memory Management Unit, peripherals, and memories.

- Created and used verification components and environments in a standard verification methodology (UVM).

- Applied verification techniques, SVA, and assertion-based verification.

- Collaborated with cross-functional teams to develop test strategies that meet customer expectations.

• Created regression tests to assess the impact of changes made to existing systems.