Madhusudhana Gopalrao Gajanaru

Motivated and enthusiastic Senior Lead Analog Layout Design Engineer with over 18 years of experience. Strong understanding of CMOS fabrication steps and Analog/Mixed Signal Layout techniques, gained through working in a fast-paced analog IC development environment. Seeking opportunities in the field of Analog Layout Design to further utilize and develop abilities, creativity, and value to the team, organization, and customer.

• Certificates of Appreciation from Texas Instruments (Dallas) for excellent contribution towards Analog IC Layout Design IPG-IPS-Analog (Dallas) team in KarMic
• Certificates of Achievement received for completing Internal Auditing of Quality Management System ISO 9001:2008 course.
• Certificates and award of Appreciation from Rambus for excellent contribution towards 7nm CXL - Prime project/ Analog Layout.

• Hands on Customize layouts for Analog Modules, DDRIOs, Buffer Chip (DB, MRDIMM), CXL and few Full Chip Circuits.
• Worked on Various CMOS technology nodes 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 130nm, 150nm, 200nm and 400nm.
• Half Year of experience in RF Chip level layout Design for 200nm Technology.
• One Year of experience in planning, execution and release on DDRIO's for 28nm, 16nm and 7nm Technology.
• Five Year of experience in planning, execution and release on Buffer Chips like DB and MRDIMM for 22nm, 12nm Technologies.
• One Year of experience in planning, execution and release on CXL (Soc Chip) for 7nm Technology.
• Good experience working on various Analog Layout designs of Differential Amplifiers, LDOs, Buck, Boost, PLL, I/O buffers, Headset Drivers, Bias generators, Clock generators, Bandgap, AFE, Receiver, Transmitter, DDRIOs, Buffer Chip modules, CXL analog modules etc.
• Excellent in debugging LVS, DRC, Antenna, Layout Back annotation, Parasitic reduction, EMIR.
• Experienced in using CAD tools: Cadence Virtuoso, Layout XL, Constraint Manager, Wire Assistant, MODGEN etc.
• Verification tools: Calibre, Assura, PVS DRC, RCX, LVS, EMIR, Antenna, etc.
• Relatively healthy experience of nearly 8 years as team leader and 3 years as a Layout Manager.
• Mentoring and imparting training on Analog Layouts to new hires and junior layout designers.
• Onsite visit to TI Dallas to coordinate Power management and PGA chip project as team lead.