MADHU SUDHAN VOMMI

Project : CincoRanch

• Worked on Spyglass DFT, responsible for generating sgdc constraints and bringing up Scan coverage (stuck-at).
• Worked on Scan insertion from scratch level by adding DFT ports at wrapper level and debugging scan DRCs.
• Worked on ATPG for both stuck-at and at-speed, pattern generation and coverage improvement to the required level.
• Worked on ATPG GLS, responsible for both chain integrity and parallel patterns validation, debugging the X and binary mismatches in no-timing simulations.
• Basic idea on MBIST insertion and simulation (Intel MINT flow) both block and top level.

Project : ODC

• Worked on ATPG, responsible for stuck-at & at-speed pattern generation and Coverage debug.
• Responsible for Scan DRC debug and stitching the Scan chains.

Project : Horse Creek

• Done scan insertion and pre-dft drc rule check
• Analyzed and debugged uncontrollable clock (D1) and set/reset (D2/D3)violations
• Done block level Pattern generation
• Worked on Coverage analysis and improvement of Coverage
• Debug done for T3,T5,T9 violations faced in ATPG
• Worked on both timing and no-timing simulations
• Faced binary and X-mismatches in the Simulations
• Done changes in test proc file and executed the pattern generation and simulation
• Faced SDF annotation issues
• Debugged the issues by annotating the delays for timing simulations

Project : BOXSTER

• Inserted the scan and checked for pre-dft drc rules
• Debugged D1,D2 and D3 violations in Scan insertion
• Pattern generation for stuck at & transition fault models
• Debugged T3,T5 trace violations in ATPG
• Coverage improvement of stuck to 99% & transition to 93%
• Improved the coverage by analyzing Pin constraints,black boxes and sequential depth
• Simulations (No-timing & Timing).

Project : PVCBU

• Pre-scan checks using Spyglass at Block level
• Scan insertion at Block level and DRC clean up
• Pattern generation and the Coverage report generation
• ATPG Coverage improvement.
• Validation of patterns at different corners
• Debugged zero delay simulations.

Project : Rennell

• Worked on Simulations (No timing)
• Chain test (unit delay, min, max) corners debug done for serial and parallel simulations
• Performed chain test parallel/serial and capture test parallel and serial.