Mahammad Hussain Dudekua

CXL 3.0 Controller IP Verification

• Understanding of Link Layer Specification of CXL 3.0
• Working for removing of unnecessary masking of signals in TB.
• Working on the regression stabilization part ie. debugging the failures.
• Adding the new assertions for Channel Interfaces.

PCIe Physical Layer VIP development

• High level understanding and Good knowledge on PCIe Protocol[Transaction Layer,Data Link Layer,Physical Layer]
• Completed the understanding of PCIe specification from the Mindshare Specification.
• Currently preparing the Verification plan for Physical Layer VIP development.
• Knowledge on LTSSM
• Knowledge on PIPE Interface
• Implemented the Testbench Architecture for PCIe VIP.
• Listed down the testcases related to the LTSSM.

SOC Verification - PCIe and CXL based Memory Expander Chip

• Worked on the register access with write and read data's comparison of multiple blocks.
• Worked Used the predefined tasks of RAL model for the register access.
• Worked on the SOC Initialisation FSM verification by developing sequence checkers and Assertions.
• For the system control, FSM needs to be verified with all of its states must be enabled during Initialisation flow.
• Developed the Assertions for all available clocks to verify Time Period, Duty Cycle, X propagation check, Enable clock and Disable clock check.
• Developed the Assertions for correct clock frequency generation with different clock divider settings and from different sources with maximum and minimum frequency generation.

AMBA - AXI4 VIP development

• AXI4_SLAVE VIP Environment with APB Master (register configuration). Implementation of slave UVC architecture and APB-Master.
• Verifying the Master DUT(DMA Engine) using AXI_Slave VIP(APB-3 Master) environment.
• Implemented UVM_Events for having control on dependency signals.
• Implemented Nested sequence with Defines to control sequences(out-standing, out-of-order, interleaving and multiple transactions).
• Implemented a virtual sequence and sequencer to control sequences and the sequencer at the top level.
• Executed the Test cases Regression list to verify DUT Functionality.
• Implemented the Automated checks in write and read monitors and controlled using reporting mechanisms.
• Implemented Timeout conditions for dependency signals.
• Implemented RAL for APB Register Configuration.
• Reported the bugs in the DUT version.
• Implemented the functional coverage for AXI4.
• Implementation of assertion for AXI4 VIP.

AMBA - APB VIP development

• Verified the protocol with single master and single slave environment.
• Implementation of AMBA APB UVC architecture.
• Implemented Functional coverage model.
• Understood the APB protocol specification.
• Developed slave logic to drive by the master.