Mahanth Venkata Sumanth Kondaveeti

• To be a good Physical Verification Engineer in VLSI Industry, and to master my skills and knowledge, and work hard for the success of organization.
• Hands on Experience with TSMC 3nm, 5nm & 6nm as part Physical Verification Worked on Block level Physical Verification Tasks.
• Good knowledge on Fixing Base DRCs, Metal DRCs and LVS Part Worked on Fixing LUP issues, IR Issues and Antenna Issues.
• Good knowledge on Fixing VSI and PercCNOD and CPODE issues 3.5 months of Training Experience in Analog layout Design.
• Worked on GPDK 45nm, TSMC 130nm. Worked on floor planning, placement and routing of analog and digital blocks.
• Familiar with DRC, LVS and QRC checks. Familiar with Standard Cell Creation. Worked on Deep N-well Concept. Knowledge on Latch up, Antenna Effect, Second Order Effects and deep sub-micron effects. Experience on Virtuoso - L & XL.
• Experience on Verification tools like Assura and Pegasus. Hands on Experience with TSMC 3nm, 5nm & 6nm as part Physical Verification Worked on Block level Physical Verification Tasks .

• Phased Locked Loop(PLL)

Role : Layout Engineer, Cadence Virtuoso-XL, Pegasus, GPDK45nm, 

Summary : A PLL is used for frequency control with a voltage or voltage-driven oscillator that constantly adjusts to match the frequency of an input signal. PLLs are used to generate, stabilize, modulate, demodulate, filter or recover a signal from a "noisy" communications channel where data has been interrupted. I was involved in layout generation of Charge Pump from Schematic, Floor Planning, Power Managementand Cleared DRC and LVS. 

Matching the Mismatches to meet the Same Delay, Placement of Dummies, taking more care on Latch-up Issues, Antenna Effect, Electron Migration and Providing Shielding for Critical Nets. 

• Digital to Analog Converter (DAC)

Role: Layout Engineer, Cadence Virtuoso-XL, Pegasus, GPDK45nm,

Summary:  It is used to convert digital to analog, developed a DAC for 8 bits by using R-2R ladder network Worked on Floor plan, Routing and Power planning and Cleared DRC and LVS. Resistors Matching, Matching the Mismatches to meet the Same Delay, Placement of Dummies, taking more care on Latch-up Issues, Antenna Effect, Electron Migration. Band Gap Reference (BGR), 1, Layout Engineer, Cadence Virtuoso-XL, Pegasus, GPDK45nm.

 It is used to generate reference voltage that is insensitive to PVT variations. Developed Layout from Schematic, Floor plan of the block and Routing and Cleared DRC and LVS. Applying Matching Techniques for BJT's and Resistors, taking more care on Latch-up Issues. Providing Guard Rings and Drawing the Layout in optimized way. 

• Operational Amplifier (Op-Amp)

Role:  Layout Engineer, Cadence Virtuoso-XL, Pegasus, GPDK45nm, 

Summary: The design involves amplification scheme, the biasing involved strengthening of low-voltage critical signals to high-voltage domain equivalent. Current mirrors and differential pairs are prominent in the design. Worked on Floor plan, Routing and Verification for block and Cleared DRC and LVS. Matching parasitic cap on Vinn Gain and Vinp Gain nets in differential pair with the help of QRC extraction. 

Minimum Poly Routing, Matching the Current Mirrors and Differential Pair, taking more care on Latch-up Issues and parasitic, Providing Guard Rings, providing different voltages for different wells and Drawing the Layout in optimized way. 

• Level Shifter

Role: Layout Engineer, Cadence Virtuoso-XL, Pegasus, GPDK 45nm, 

Summary: It is a circuit used for voltage level shifting from one voltage domain to another voltage domain. Taken care of isolation between different voltage domains optimally. Used Deep N- well concept to isolate the bulks of two different potentials. 

• Standard Cells

Role: Layout Engineer, Cadence Virtuoso-L, Assura, TSMC 130nm.

Summary : Worked on designing standard cells like INV, AND, OR, NAND, NOR, EX- OR, MUX and DFF. To draw in Minimum Width using Single Metal, Optimizing the Cell and maintaining Cell Height in terms of Metal2 Pitches, following Half DRC rules. Maintained continuous diffusion wherever possible to minimize the area & for power efficiency. Minimum Poly routing used wherever possible. ICC2, 3 nm .

Good Knowledge on Block level PhyV checks, Base & Metal DRC, LVS Check. Worked on signoff checks, Dynamic IR, Antenna issues Addressed by Moving cells into the correct domain ICC2, 5nm/15 Layers. Worked on block level LVS checks and Fixings Good Knowledge on Fixing Base DRC’s and Metal DRC’s Worked On Antenna issues. 

Good Knowledge on Softcheck Issues ICC2, 6nm/13layers, Worked on Fully Block level Physical verification Tasks in floorplan, Routing and ECO Stage Good Knowledge on fixing Base DRCs and Metal DRCs Worked on LVS checks likes Shorts, hierarchical Shorts, Opens. Manually Fixing Antenna issue Innovus, 28nm/9Layers. Good Knowledge on Block level PhyV checks, Base & Metal DRC, LVS Check. Worked on signoff checks, Dynamic IR, Antenna issues Addressed by Moving cells into the correct domain.

I hereby declare that the above-mentioned details are correct according to my knowledge and bear the responsibility for the correctness of the above-mentioned information.