Mahesh Gk

Skilled in Analog Layout Design Engineering with focus on developing complex analog and mixed-signal integrated circuits. Strong background in various technologies including CMOS. Understands design rules, device matching, low power techniques, parasitic reduction strategies and floor planning. Proven track record of optimizing designs for performance, manufacturability and testability.

Overall, 11+ years of Industry experience

• 6.6 years of dedicated Technical experience in VLSI - Analog Layout Design
• 4.5 years of dedicated Non-Technical experience in Facilities & Global Procurement

English, Hindi, Kannada & Telugu

• Reading books/Novels
• Painting/Sketches
• Listening to music
• Playing Cricket, Badminton & TT

• TSMC 3nm, 5nm, 6nm, 7nm, 22nm
• INTEL 7nm, 10nm
• Samsung 14nm
• UMC 180nm

• Cadence Virtuoso
• Intel Genesys
• Mentor Graphics Calibre

Medusa DDRSSB RX Macros 

Client: AMD

Technology:  TSMC N3

Duration: 3 Months
Responsibilities:
 N3P is a technology where 2 different std cell height devices will be placed in
combination in the macros
 POC for RX domain which has 4 macros consists of DDR & SDR for CLK & DATA paths
and 2 DECAPS
 Meeting DECAPS requirements
 Floorplan, Placement, Routings and LV cleanup for SSB Rx Macros.
 Taking care of matching & shielding for CLK routings
 Worked on standard custom cells.
 Multiple bits Bump placement with PHYLET routings

Badri DDRSSB  RX Macros

Client: AMD

Technology: TSMC N7

Duration: 1 year
Responsibilities:
 POC for RX domain which has 4 macros consists of DDR & SDR for CLK & DATA paths
and 2 DECAPS
 Floorplan, Placement, Routings and LV cleanup for SSB Rx Macros.
 Meeting DECAPS requirements
 Worked on standard custom cells.
 Multiple bits Bump placement with PHYLET routings

Navi4x DDRSSB DLL Macros 

Client: AMD

Technology:  TSMC N5

Duration: 3 Months
Responsibilities:
 Floorplan, Placement, Routings LV cleanup for SSB Macros.
 Worked on standard custom cells.
 PHYLET tasks where bumps connected

Aria 6nmRF

Client: Qualcomm

Technology: TSMC N6 RF

Durations: 6 Months
Responsibilities:
 PLL Charge Pump & other PMU ctrl blocks - Floorplan, Placement, Routings LV cleanup for the required blocks.
 Following of Layout constraints and verification's checks to meet the layout quality
 Communications with designers/leads for any layout impacts w.r.t design changes and review for better layout improvements
 Ownership for the digital blocks for all lib cells

Concerto PMU 

Client: Qualcomm

Technology: TSMC 22nm RF

Duration: 6 Months
Responsibilities:
 PMU (SMPS & ADDA interface block’s) - Floorplan, Placement, Routings & LV cleanup for all the required blocks.
 Following the Layout constraints and verifications checks to meet the layout quality
 Communications with designers for design changes updates and review for better layout improvements

MDLL CBB for OLC IP
Client: Intel

Technology: TSMC N3

Duration: 1.5 years
Responsibilities:
 Floorplan, Placement, Routing for all tires of blocks till CBB level
 Layout verification (LV Bundle) Clean up till PROD release
 LEF generation and RV check (IR drop and EM)
 Matching and Shielding constraints for critical nets
 LCO’s and ECO’s improvements based on the designer requirements for enhancing
the performance of the cell.
Challenges:
 TSMC introduced 3nm and we are the 1st batch in the company to work under this
node and faced very challenges in every step starting from the floor plan due to new layers and pdk.
 Worked on many test cases on the abutment of the different height and different
potentials cells to clean up the violations w.r.t horizontal, vertical cell abutments as 3t, 4t are the real challenges.
 Placements of all sub-blocks were inter-dependent on each other, so it was very
important to come up with a placement which satisfies all aspects
 Complete IR and EM fixes were very important for the Final PROD release.

MDLL & TX CBB for SRF IP - Sierra Forrest (Duration 1 year)

Client: Intel

Technology: TSMC N3

Duration: 1 year
Responsibilities:
 Floorplan, Placement, Routing for all tires of blocks
 Layout verification (LVS and DRC, ERC) Clean up till PROD release
 LEF generation and RV check (IR drop and EM)
 Matching and Shielding requirements for critical nets
 LCO’s and ECO’s improvements based on the designer requirements
Challenges:
 Since SRF is our 2nd project under TSMC 3nm node and we have used some of the CBB’s used in OLC by adding the new AIP’s
 Re-floorplan of the existing CBB’s without changing the size of the cell and adding of new AIP block fitting inside the CBB and routing changes with respects to new nets
 Maintaining layout standards to meet the RV

GPIO 

Client: Intel

Technology: TSMC 10nm

Duration: 4 Months
Responsibilities:
 Floorplan, Placement, and routing of sub cells.
 Layout verification – LV Bundle clean up
 Layout quality checks

Internal Project (Duration 6 months)
Description: This project was carried out internally for training purpose under Intel
7nm Technology where we need to be clean up LV bundle within the timeline by
meeting the given constraints.
Responsibilities:
 Floorplan, Placement, and routing of the cells
 LV Bundle cleanup
 Matching and Shielding constraints
Challenges:

 As part of L2 training, we took the challenges of completing the given block from scratch level to LV bundle cleanup
 Major constraints were to follow delay cells and maintain same routing distance between the delay cells for parasitic balancing.
 Layouts of individual cells top level integration of all these cells done

Project Name: “Human Machine Interface (HMI)”
Project Description: To develop a Human machine interface using the advance image processing technique in the Real-time environment. This is done using the palm movement and without pressing any buttons. This kind of human machine interfaces would allow a human user to control remotely through hand gestures a wide variety of devices.

CMOS VLSI Level 1 training under Eklakshya using UMC 180nm Technology for the period of 6 months

• Father Name: Kumar P
• Mother Name: Rajamma
• Date of Birth: 10-08-1992
• Gender: Male
• Nationality: Indian
• Marital Status: Married
• Religion: Hindu
• Address: No.211/65, Kanasu, 2nd Main Extension Kaveri Road, Padmeshwari Nagar, Bhattrahalli, K R Puram Bangalore PIN Code: 560049

I hereby, declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.