Manaswini Mishra

Enthusiastic and highly motivated recent graduate with a M.Tech in Electronics & Communication Engineering with a focus on VLSI design. Proficient in Verilog/VHDL, CAD tools like TCAD. Solid understanding of digital circuit design principles and ASIC design flow. Demonstrated ability to work effectively in team environments through academic projects and internships. Eager to apply theoretical knowledge to practical applications in the field of VLSI design.

• Certificate of Completion in SAP ABAP(TAW10,TAW12,NetWeaver 7.5)
• SAP Student Academy
• VLSI SoC Design using Verilog HDL (03/2022) Maven Silicon
• Python-Basic to Advance
• TCAD
• Satellite based Navigation A journey from GPS to Mobile Phone Platform-IIRS,ISRO,Dehradun,uttarakhand
• Cisco Networking Academy

• Design and Analysis of 7 nm node Gate-Stack Tri-gate FinFET for Mixed Signal Applications -Presented and published a IEEE
  conference Paper during my 2nd Semester - Sept, 2023

• Double gate junction underlap dual gate finfet for RF and analog applications - Presented a springer conference Paper
  during my 3rd Semester, Jan, 2024