MANDULA SHARATH
Overview
1
1
year of professional experience
6
6
years of post-secondary education
Work History
Class Representative, ECE branch
Integrated Engineering
07.2014 - 05.2015
- 1.Persued a degree from Indian School of Business in Design thinking phase
- 2.Secured 1st and 2nd positions in regional and state level science fair
- 3.Selected for AP IIITs, Programme for being in top in SSC Examination 2010
- 4.Principals best student award for being topper of the school in SSC Examination
- EXTRA-CURRICULAR 1.Co-founded Blood Box a non-profit organization to help those who need blood urgently
- 3.NCC cadet with A grade certificate
- 4.Got gold medals in Cricket, Kabaddi held in Kakatiya University
- 5.Worked as a Webcasting Engineer in Andhra Pradesh state bye-Elections for 3 times
- 6.Conducted and participated in Plantation, blood donation, rallies and several other activities of NSS
- RGUKT, Baser.
Education
M.Tech - Microelectronics and VLSI Design, Electrical Communication Engineering (ECE
Indian Institute of Science
B.Tech - Electronics and Communication Engineering
Kakatiya Institute of Technology and Science Warangal
01.2012 - 01.2016
XII - undefined
01.2010 - 01.2012
Class X - undefined
RGUKT IIIT
Skills
TECHNICAL STRENGTHSundefined
Accomplishments
- Residential School Sarvail 94.83 %
- PROJECTS
- M.Tech Project:Optical Current Sensors
- Advisor:Asst.Prof.Varun Raghunathan,IISc
- Optical Sensors uses interferometers (MZI) to measure electrical currents.A piezoelectric material(PZT) is coated on the integrated waveguide of the MZI.PZT material create stress on waveguide due to applied voltage, which changes the effective refractive index.The change in phase at the interferometer output is observed due to change in refractive index, which is a function of the input current
- INTERNSHIP: TEXAS INSTRUMENTS BANGALORE
- Hybrid PLL Model:The hybrid PLL architecture combines a linear analog path and bang-bang digital integral path.In hybrid PLL the proportional path retains its analog characteristics as like in analog PLL and the integral path is implemented digitally using a bang-bang phase detector.The digital implementation of the integral path keeps the PLL small, programmable and scalable and it avoids usage of large low leakage capacitor to perform integration
- COURSE PROJECTS: 1.Two Stage Op-Amp Design:Designed a two stage Op-Amp topology in 65nm CMOS technology with given specifications.Simulations are done using Cadence Virtuoso
- 2.Hardware Selection Sort:Designed a hardware to sort 8 bit numbers stored in an array
- Core functionality can consist of a variable length array
- B.Tech Project:
- Pattern Synthesis Using Amplitude Control Method:To design an array to produce sector beams with reduced faraway side lobes for desired beam width.An attempt is made to produce them with the introduction of amplitude distribution with zero phase.The work is useful to produce sector beams with reduced faraway side lobes, which controls the jamming effects effectively
- COURSES
- Analog VLSI Circuits,Digital VLSI Circuits,Basics of Semiconductor Devices and Technology,Radio
- Frequency Integrated Circuits and Systems,Digital System Design with FPGA,CAD for High Speed
- Circuits,Control System Design
- Online Courses:Basic Electrical Circuits,Analog IC Design, Analog Circuits by Nagendra Krishnapura (NPTEL).
Timeline
Class Representative, ECE branch
Integrated Engineering
07.2014 - 05.2015
B.Tech - Electronics and Communication Engineering
Kakatiya Institute of Technology and Science Warangal
01.2012 - 01.2016
XII - undefined
01.2010 - 01.2012
M.Tech - Microelectronics and VLSI Design, Electrical Communication Engineering (ECE
Indian Institute of Science
Class X - undefined
RGUKT IIIT
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