Mangu Venkata Krishna Kalyan

Advanced VLSI Design and Verification Course:
Maven Silicon VLSI Design and Training Center, Bengaluru | Jan 25, 2023 till date

1) VLSI Domain Skills

• HDL: Verilog
• HVL: SystemVerilog
• Verification Methodologies: Constraint Random Coverage Driven Verification
  Assertion Based Verification - SVA
• TB Methodology: UVM
• Protocols: AXI, AHB, UART, I2C, SPI
• EDA Tool: Mentor Graphics - Questasim and Xlinix - ISE, Xilinx -Vivado
• RTL linting: VC Spyglass tool
• Domain: ASIC/FPGA front-end Design and Verification
• Programming Languages: C [Datatype | Array | Pointers | Memory Allocation | List |Queues and stacks | Data structure, Functions]
  C++ ( Good knowledge of OOPs concept, Class, Inheritance, Polymorphism ),Python
• Operating System: Working knowledge of Windows and Linux
• Scripting Languages: Perl Scripting,Python Scripting
• Core Skills: RTL Coding using Synthesizable constructs of Verilog, FSM based design, Simulation, CMOS Fundamentals, Code Coverage,
  Functional Coverage, Synthesis,Static Timing Analysis, Assertion Based Verification using SystemVerilog Assertions.

2) VLSI Design Skills

• Digital Electronics :
  Combinational & Sequential circuits, FSM, Memories, CMOS implementation, Stick diagram,
• STA :
  STA Basics, Comparison with DTA, Timing Path and Constraints, Different types of clocks ,Clock domain and Variations, Clock Distribution Networks, Fixing timing failure
• Verilog Programming :
  Data types, Operators, Processes, BA & NBA, Delays in Verilog, begin - end & fork join blocks,looping & branching construct, System tasks & Functions, compiler directives, FSM coding,Synthesis issues, Races in simulation, pipelining RTL & TB Coding,
• Advanced Verilog & Code Coverage:
  Generate block, Continuous Procedural Assignments, Self-checking testbench, Automatic Tasks ,Named Events and Stratified Event Queue, Code Coverage: Statement and branch coverage,Condition & Expression Coverage, Toggle & FSM Coverage.

3) Verification Skills

System Verilog HVL:

• Memories - Dynamic array, Queue, Associative array, Task & Function - Pass by reference
• Interface - Modport and clocking block
• Basic and advanced object-oriented programming - Handle assignments, Copying the object contents, Inheritance, polymorphism, static properties and methods, virtual classes and parameterized classes.
• Constraint Randomization - constraint overriding and inheritance, Distribution and conditional constraints, Soft, static and inline constraints.
• Thread synchronization techniques - events, semaphores and Mailbox - built-in methods
• Functional coverage - Cover groups, bins and cross-coverage, CRCDV and regression testing

System Verilog HVL:
Interface and clocking block, Inheritance and Polymorphism, Constraint randomization - Inline, distribution, conditional, soft and static constraints. Mailbox and semaphores, Functional coverage, CRCDV and regression testing.

System Verilog Assertions:
Types of assertions, assertion building blocks, sequences with edge definitions and logical relationship. Sequences with different timing relationships. clock definitions, implication and repetition operators, different sequence compositions, inline and binding assertions, advanced SVA Features and assertion Coverage

UVM:

• UVM Objects & Components
• UVM Factory & overriding methods
• Stimulus Modelling
• UVM Phases
• UVM Configuration
• TLM
• UVM Sequence, virtual sequence & sequencer
• Introduction to RAL

4) College skills

Tools used in Engineering:

• MATLAB - Digital Signal Processing
• Keil MDK or Arduino IDE - Microcontroller Programming
• MASM or TASM - Assembly Language Programming (8085 or 8086) etc
• LTSpice & HSpice(Spice Simulator ) - Circuit analysis

Subject Expertise:
Digital electronics, Analog electronics, Network analysis, Analog & Digital Communications, Signals & System, Signal Processing, Microprocessors/ Microcontrollers, Computer Architecture and Organization

VLSI Projects

1) Router 1x3 – RTL design and Verification

• HDL: Verilog
• HVL: SystemVerilog
• TB Methodology: UVM
• EDA Tools: Questasim and ISE
• Description: The router accepts data packets on a single 8-bit port and routes them to one of the
  three output channels, channel0, channel1 and channel2.
• Responsibilities:
  ➢ Architected the block level structure for the design
  ➢ Implemented RTL using Verilog HDL.
  ➢ Architected the class based verification environment using SystemVerilog
  ➢ Verified the RTL model using SystemVerilog.
  ➢ Generated functional and code coverage for the RTL verification sign-off
  ➢ Synthesized the design.

2) RISC - V Design:

The RV32I Processor is designed to support all RV32I Base Integer Instructions (Total -39). It’s a three stage pipelined processor which executes 32 bit instructions in program order.
Pipelined Stage I - The instructions are fetched from memory.
Pipelined Stage II - The instructions are decoded and the control signals for all units are generated. Branches, jumps and stores are executed in advance in this stage
Pipelined Stage III - Executes complete instruction and writes back the results in the register file

Responsibilities for Design:
➢ Developed RTL codes for all modules of RISC V processor.
➢ Verified individual modules with Linear TB code
➢ The top module is synthesized and simulated

RISC-V Verification

The RV32I Processor is designed to support all RV32I Base Integer Instructions (Total -39). It’s
a three stage pipelined processor which executes 32 bit instructions in program order.
Pipelined Stage I - The instructions are fetched from memory.
Pipelined Stage II - The instructions are decoded and the control signals for all units are generated. Branches, jumps and stores are executed in advance in this stage
Pipelined Stage III - Executes complete instruction and writes back the results in the register file

Responsibilities for Verification:
➢ Developed a class based TB using UVM methodology.
➢ Verified all the different types of instructions by developing multiple testcases.
➢ Developed the coverage models and signed-off the verification by achieving 100% coverage

3) Spice Modeling of High-Performance design of Ternary Half Adder using GNRFET Technology -(MTech Thesis)
Description: Designing of ternary logic Half adder using futuristic devices like CNTFET (Carbon NanoTube Field Effect Transistor) and GNRFET (Graphene Nano Ribbon Field Effect Transistor) achieve ternary logic using the concept of variable threshold voltage and developed using HSPICE tool and models avialble from nano hub website.

I do hereby, declare that all the information provided above are true to the best of my knowledge and belief.
Place: Vishakapatnam
Date: 03/05/2023                                                                            M.V.K.Kalyan