MANOJ BHIMAVARAPU

Having 3.11 years of experience in SoC, Subsystem and IP level verification debugging and closure. Experience in writing test benches in system Verilog and UVM Experience in executing SV/C-based test cases and SV-UVM based environment. Knowledge on Verilog, VHDL. Experience in effort estimation, project tracking. Experience in SoC GLS verification (no-timing and timing). Experience in functional and code coverage closure. Experience in using industry standard EDA tools for the front-end design verification. Experience in I2C, SPI, GPIO, SMBus and APB protocal

• ADVANCE VLSI DESIGN AND VERIFICATION COURSE
• MAVEN SILICON VLSI DESIGN AND TRANING INSTITUTE, BANGALORE
• JAN 2020 - OCT 2020