MANOJ KUMAR
Kushinagar, U.P
Summary
Dynamic SoC Design Verification professional with extensive experience at Intel Corporation, excelling in test plan development and regression analysis. Proven ability to collaborate cross-functionally and implement comprehensive verification strategies, ensuring bug-free designs. Proficient in Verilog and Python, with a strong focus on achieving project goals and delivering high-quality results.
Overview
4
4
years of professional experience
Work History
SoC Design Verification
Intel Corporation
Bengaluru
07.2022 - Current
- Collaborated closely with team members to achieve project objectives and meet deadlines.
- Worked with cross-functional teams to achieve goals.
- Developing and implementing comprehensive test plans and verification strategies for the simulation environment to ensure the delivery of best-in-class client SoCs.
- Regression was run using the Venus tool, and the failures were analyzed and debugged to ensure the bug-free SoCs.
- Designed and developed checkers to ensure the correct functionality of the design.
- Designed and developed the functional coverage to ensure the complete coverage of the design specification.
IP Design Verification
Intel Corporation
Bengaluru
10.2024 - 06.2025
- Prioritized and organized tasks to efficiently accomplish project goals.
- Developed the tests to cover the features and ensure the bug free design
- I ran the regression using the vManager tool with AI enabled to check the end-to-end functionality of the design. Analyzed the failures and debugged it.
- Designed and developed checkers to ensure the correct functionality of the design.
- Designed and developed the functional coverage to ensure the complete coverage of the design specification.
- Designed and developed the code coverage to ensure complete coverage of RTL code.
SoC Design Verification Intern
Intel Corporation
Bengaluru
07.2021 - 06.2022
- Running the regression for the Intel server SoCs using the Venus tool, and analyzing the failure clusters.
- Developed a script in Python to analyze the first level of debug metrics, and other post-process functions after the test run.
- Full chip functional verification (simulation) for Intel server SoCs, including regression debug and functional coverage, using VCS and Verdi.
Education
Master of Technology - VLSI Design
NIT KURUKSHETRA
KURUKSHETRA06-2022
Bachelor of Technology - Electronics Engineering
KNIT Sultanpur
Sultanpur06-2018
Skills
- Test plan development
- Functional verification
- Regression analysis
- Coverage design
- Debugging techniques
- SoC architecture understanding
- Cross-functional collaboration
- Task prioritization
- Problem solving
- Scripting: Perl, Python, Shell
- Verification skills: Verilog, SV, UVM
- Verification tools: Verdi, VCS, Venus, vManager
- Programming skills: C, C, Python
- Protocols: AXI, APB, AHB
Timeline
IP Design Verification
Intel Corporation
10.2024 - 06.2025
SoC Design Verification
Intel Corporation
07.2022 - Current
SoC Design Verification Intern
Intel Corporation
07.2021 - 06.2022
Master of Technology - VLSI Design
NIT KURUKSHETRA
Bachelor of Technology - Electronics Engineering
KNIT Sultanpur
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