Meghashree Doddamani
Bengaluru
Summary
DevOps Engineer with over one year of experience in designing and automating cloud-native infrastructure. Expertise in AWS, Kubernetes, and Terraform, focusing on building secure and highly available systems. Proven track record of enhancing deployment speed and operational efficiency through CI/CD practices. Strong collaboration skills with a commitment to optimizing development workflows in Agile environments.
Overview
5
5
years of professional experience
5
5
Certifications
Work History
DevOps Engineer
MicroDegree
Bengaluru
12.2024 - 01.2026
- Designed and automated cloud-native infrastructure at scale using AWS, Kubernetes, and Terraform.
- Engineered CI/CD pipelines with GitHub Actions and Jenkins, increasing deployment frequency.
- Implemented comprehensive monitoring solutions with Prometheus, Grafana, and AWS CloudWatch to enhance incident response times.
- Automated deployment processes using Jenkins and GitLab, streamlining transitions from development to production.
- Managed AWS cloud infrastructure to ensure peak performance and security across applications.
- Collaborated with development teams to optimize application delivery workflows and reduce deployment bottlenecks.
- Implemented security protocols to protect data and maintain compliance standards.
- Assisted in configuration management using version control systems effectively.
- Documented processes and procedures for improved team knowledge sharing.
PLANNED CAREER BREAK
Health & Wellness
Bengaluru
09.2023 - 11.2024
- Dedicated time to full-time caregiving, fostering adaptability and commitment.
- Achieved multiple certifications through remote education, showcasing effective self-management.
- Exhibited exceptional focus and determination while pursuing professional development.
VLSI Design Engineer
D2S, Inc
Bengaluru
04.2021 - 08.2023
- As a Memory Layout Design Engineer was responsible for the physical implementation and optimization of memory IPs, transforming circuit schematics into silicon layouts for technologies like SRAM, ROM, and Register Files.
- Worked on advanced sub-nanometer nodes (3nm/5nm) and complex FinFET architectures undertaking refined layout automation scripts to accelerate memory IP generation, enhancing design consistency and reducing manual intervention across SRAM and ROM projects using Cadence Virtuoso (layout editing) EDA Tool.
- Core Responsibilities
- Physical Layout Implementation: Design transistor-level layouts for memory bitcells, sense amplifiers, row/column decoders, and control blocks.
- Block Integration: Perform top-level integration of memory leafcells into complete arrays and integrate memory GDS into larger System-on-Chip (SoC) environments.
- PPA Optimization: Balance Power, Performance, and Area (PPA) while ensuring high yield through layout matching, symmetry, and parasitic control.
- Physical Verification: Run and debug sign-off checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), Electrical Rule Checks (ERC), and Antenna/Density checks.
- Reliability Analysis: Address electrical and reliability issues such as Electro-migration (EM), IR drop, and Electrostatic Discharge (ESD) violations.
- Compiler Development: Support memory compiler automation, creating reusable leafcell libraries that generate tailored memory instances.
Education
Mtech - VLSI
RV College of Engineering
Bengaluru01.2020
Skills
- DevOps and cloud computing
- Automation tools and scripting
- CI/CD pipeline development
- Infrastructure automation
- Security compliance
- Configuration management
- Team collaboration
- Problem solving
- Project coordination
- Adaptability to change
- Software deployment
- Monitoring tools
- Containerization technologies
- API integration
- Version control systems
- Continuous delivery practices
- Disaster recovery strategies
- Data connectivity solutions
- Application performance tuning
- Systems design support
- Agile methodologies
- AWS management
- Kubernetes orchestration
- Terraform automation
Languages
- English
- Hindi
- Telugu
- Kannada
Personal Information
- Father's Name: Padmanabha
- Mother's Name: Kalavati
- Date of Birth: 10/07/1995
Languages
English
Advanced (C1)
C1
Hindi
Advanced (C1)
C1
Kannada
Native
Native
Telugu
Upper Intermediate (B2)
B2
Certification
Certified AWS Cloud Practitioner
Accomplishments
D2S Innovative Employee award Q3- 2022
Affiliations
State Level Basket Ball Player
Timeline
DevOps Engineer
MicroDegree
12.2024 - 01.2026
PLANNED CAREER BREAK
Health & Wellness
09.2023 - 11.2024
VLSI Design Engineer
D2S, Inc
04.2021 - 08.2023
Mtech - VLSI
RV College of Engineering