Summary
Overview
Work History
Education
Skills
Projects
Accomplishments
Timeline
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Mimoni Das

Bengaluru

Summary

Detail-oriented PDK QA Engineer with 3 years of experience in Process Design Kit (PDK) validation and semiconductor design flow verification. Proven expertise in validating advanced technology nodes (1.8nm, 3nm, 5nm, 7nm) with strong command of Calibre, Virtuoso, and ICV for DRC/LVS/PEX compliance. Skilled in analog layout fundamentals, PDK feature validation. Adept at debugging parasitic effects, resolving layout violations, and ensuring quality signoff. Actively seeking opportunities in PDK QA or Analog Layout Design, bringing technical depth and a precision-driven mindset.

Overview

4
4
years of professional experience

Work History

PDK QA Engineer

Intel Corporaton
Bengaluru
06.2022 - Current
  • Validated and released foundry PDKs for 1.4nm, 1.8nm, 3nm, 5nm and 7nm nodes ensuring robust DRC/LVS/PEX compliance and QA coverage.
  • Designed and implemented analog layout test structures (e.g., resistor arrays, matched pairs, current mirrors) to verify PDK feature functionality.
  • Performed schematic-to-layout QA verification and evaluated LVS/DRC/antenna violations using Calibre and Virtuoso.
  • Demonstrated strong expertise in resolving complex DRC, LVS, and antenna violations across analog and mixed-signal layouts.
  • Collaborated cross-functionally with layout, PDK, and foundry teams to debug parasitic extraction, LDE, and reliability issues.
  • Contributed to QA of layout-dependent effects (LDE), EM/IR, and reliability rules for Intel’s foundry PDKs.
  • Developed detailed documentation covering QA methodology, regression reports, layout test coverage, and signoff guidelines.

QA Engineer – Intern

Intel Corporaton
Bengaluru
08.2021 - 05.2022
  • Supported internal PDK QA workflows and integration with customer EDA environments.
  • Executed nightly regression testing on OpenAccess-based design flows and analyzed QA logs for LVS/DRC/PEX violations.
  • Proposed fixes and improvement plans for observed rule deck failures during Kit QA.

Education

M.Tech - VLSI Design

Vellore Institute of Technology
Vellore
01-2022

B.Tech - Electrical Engineering

Rashtrasant Tukadoji Maharaj Nagpur University
Nagpur
01-2018

Skills

  • PDK & QA: Foundry PDK validation, DRC/LVS/PEX checks & antenna rule coverage
  • Analog Layout: Layout matching techniques, shielding, symmetry & parasitic
  • EDA Tools: Cadence Virtuoso, Calibre (DRC/LVS/PEX), Synopsys ICV
  • Scripting: Python, Tcl, Shell scripting
  • Other Tools: Bug tracking (JIRA) & QA documentation

Projects

  • Designed and successfully completed signoff for analog layout blocks: Current mirror, Differential pair, Low Dropout Regulator (LDO), Passive Low-Pass Filter, PLL , BGR in 1.8nm technology.
  • Applied industry best practices for matching, symmetry & shielding.
  • Performed layout verification using Cadence Virtuoso, Synopsys ICV, and Mentor Calibre.
  • Ensured compliance with DRC/LVS rules, parasitic extraction and layout robustness.

Accomplishments

  • Qualified in GATE EE – 2020
  • Strong interest in analog layout optimization and DFM practices.

Timeline

PDK QA Engineer

Intel Corporaton
06.2022 - Current

QA Engineer – Intern

Intel Corporaton
08.2021 - 05.2022

M.Tech - VLSI Design

Vellore Institute of Technology

B.Tech - Electrical Engineering

Rashtrasant Tukadoji Maharaj Nagpur University

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Mimoni Das