Mirza Afsar Baig

Responsibility:

• Handling RTLFP(Design Planning for mcchanmse subsystem inside IMH-D chiplet).
• Delivered quality collaterals for 0p3 phase to Partition Owners for PNR implementation.
• Working with CB2 truck planning team to implement high-speed clock as top-down.
• Working on TIP(Topological Interconnect Planning) automation and resolved many HFN nets in RTLFP to ease place_pins.
• Worked on preparing automation TCL procs to extract HFN ports and point-to-point port connection to ease pin placement.

Technology: Intel 4

Tools: Fusion compiler(RTLFP,TIP)

Responsibility:

• Handled full RTL to GDSII flow for 2 Partition(parsocvmchsftop,parsocvmshfbot) at 0p8 stage.
• Worked on closure of all signoff's(FEV,VCLP,caliber,RV,DRC,power,timing closure) to meet 0p8 exit quality.
• Provided Feedback on Healthchecks,port SRSN to resolve ISO* VCLP issues,port placement to improve interface timing for 1p0.

Technology: Intel 20A

Tools: Fusion Compiler-APR-FC,Primetime,Intel Caliber,VCLP,ICV,Onepower,LEC Conformal,Redhawk,timing_lite,star_pv

Responsibility:

• Executed critical RTL logical ECOs for GPIO partition and worked on signoff closure.
• Carried out multiple timing,caliber ECO's for 2 partition (parclk,cguaips) and worked on closure of all signoffs.
• Implemented logical ECOs in RTLFP for both NAC and 2xNAC subsystems and delivered the required collaterals to partition owners. Parallelly worked on closure of FEV and VCLP signoff for B0 Stepping.
• Worked with Synopsys Team to implement DSO.ai(Design Space optimization) on few partition and prepared recipe to reduce APR exit turn around time.

Technology: Intel 4

Tools: Fusion Compiler(APR_FC,RTLFP), VCLP, LEC Conformal ,Redhawk,ICV,DSO.ai,intel caliber,primetime,onepower

Responsibility:

• Handled full RTL to GDSII flow for gpio partition along with all signoff i.e. FEV,VCLP,Timing Closure,RV,DRC,Caliber.
• Handled RTLFP(Design Planning) for 1 Subsystem 2xNAC having 11M instances in all aspects (partitioning,pin placement,pg creation,integration),deilvered quality collaterals to Parition owners and closed Subsystem FEV,VCLP.Given timely pd_intent to SOC and worked on closure of RV,DRC at subsystem level.
• Supported RTLFP(Design Planning) for another subsystem NAC in all aspects (partitioning,pin placement,pg creation,integration),deilvered quality collaterals to Parition owners and closed Subsystem FEV,VCLP.Given timely pd_intent to SOC and worked on closure of RV,DRC at subsystem level.
• Worked with CB2 Team (Top down clock trunk planning for high speed clock) ,given timely feedback to get quality collaterals.
• Worked with SOC team for placement of IDV/DIC/ODI/VDM placement at subsystem level taking care of placement guidelines.
• Worked with Analog signal routing team and implemented topdown analog routes along with placement of diode,dts cells.
• Worked with RTL team and given timely feedback withrespect to unfeasible connectivity,long detouring paths causing timing violations.

Technology: Intel 4

Tools: Fusion Compiler-(APR-FC,RTLFP), VCLP, LEC Conformal ,Redhawk,ICV,Intel caliber,Primetime,star_pv,onepower

Responsibility:

• Implemented Partitioning for 11 blocks from RTL to GDSII
• Generated IO constraints for partitions from subsystem level and have done analysis on resolving io delay issues with block owners
• Pin Planning taking care of Feedthru,UPF Validation
• Responsible for FEV, VCLP, Timing Budgeting, DRC/LVS activities, RDL Routing, Bump Analysis, RV.
• Interacted with clock building team and used custom clock routes at the Subsystem Level, pushing them down to the block level.
• Integration of Subsystem.

Technology: Intel 4.

Tools: Fusion Compiler-RTLFP, VCLP, LEC Conformal ,Redhawk,ICV

Design Details: 11 Partition having 5 MI (Multi instantiated)partition, 2 Ghz clock coming to 1 partition and got distributed to other partition as 1Ghz and 500 Mhz, 15 Million Gate count,2659 Ports, 11 clocks, 15 metal Layers + RDL layers, Low power Design with multi domain.

Challenges: Closing partition shapes with their desired utilization, consuming UPF in subsystem level having MI partition with Multi domain, controlling unwanted feedthrough ports created, resolving improper lib mapping at compile stage, timing estimation for IO generation, resolving SRSN issue, PG creation issue.

Responsibility:

• Have implemented RTL to GDSII of partition.
• Have done multiple floorplanning to improve congestion, pin density, cell density, and utilization.
• Have Multiple experiments with different app option settings,path grouping,macro placement change,bound creation for reducing high logic depth
• Worked with Clock team to get good quality of clock collaterals(SDC) inorder to close unconstrained sequentials
• Worked with DP team for contraining all ports with desired io delays for closing io paths
• Have done timing correlation analysis between PT & APR
• Applied various strategies to reduce skew and latency at cts stage
• Fixed trans and timing violation across various corners
• Applied various techniques inorder to reduce power consumption
• Have done analysis for false paths,multi-cycle paths ,and given feedback to clock team to validate clock collaterals(SDC)
• Responsible for signoff runs DRC/LVS,Primetime,RC- extraction,power,caliber,FEV,VCLP,RV.

Technology: 7nm

Tools: Fusion Compiler-APR-FC,Primetime,Intel Caliber,VCLP,ICV,Onepower,LEC Conformal,Redhawk,TIMCAT,star_pv

Design details: 1.5 M instances, 1 Ghz frequency main clock, 30 macros,1 DOP,656 ports,5 clocks,15 metal layers,multidomain design.

Challenges: Design having high logic depth ,created path groups giving weightage.Congestion issue,have tried multiple floorplan with partial blockage,keep out margins,shorts with power switching cells ,analysed and optimized usage of lvt and hvt for power reduction

Responsibility:

• Implemented Partitioning for 11 blocks from Netlist to GDSII using correct lib version of 5 reused partition
• Intracted with clock building team and implemented CB2 clock routes from Subsystem Level and Push down to block level ensuring proper logical connectivity without any overlap with adjacent reused partition
• Responsible for Bump planning for subsystem,interacted with SOC team,created tm0/tm1 routing having bump aligned with those routes
• To make proper power physical connectivity with reused partion have done Port-up to drop vias
• Involved in hip version validation,subsystem UPF validation with partition UPF related to PST table
• Involved in ESD/PRS/ODI/VDM cell placement suggested by SOC in partition level
• Have done multiple iteration to control feedthrough ports creation,involved in clearing health check issues at pin place stage
• Responsible for signoff activities FEV,Spyglass-LP,RV,LV,RC extraction after integrating for Full chip timing run
• Interacted with LV team to clear issues like shorts,opens,floating,DRC,v1up,density violation after integration at subsystem level
• Interacted with RV team to clear issues like S-factor,electromigration(EM),SH,IR drop issue at subsystem level
• Involved in APR implementation of 4 physical only partition which got placed in channel between 2 subsystems in TNR SOC
• Involved in CB2 clock pushdown in correct power domain with proper hierarchy in another subsystem Parnec in TNR.

Technology: 10nm

Tools: ICC2-DP,LEC Conformal,Spyglass-LP,Redhawk,ICV

Design details: 11 partition,1 analog IP,1.2 Ghz clock frequency,32 clocks,5 partition APR implementation from Netlist to GDSII,6 partition are reused from earlier version,11 layers+RDL layers,multivoltage with multi power domain,1 PLL inside a partition,C4 bump.

Challenges: CB2 clock routes validation logically and physically,controlling unwanted Feedthrough ports, Power routing at subsystem taking care at internal partition PG routes also some analog routes with some shielding to avoid crosstalk ,Top Level LVS,RV issues related to IR drop.

Responsibility:

• Responsible for running signoff runs, i.e.
• FEV,Spyglass-LP,XOR- Spec,LV,primetime,caliber for cmd block
• Involved in clearing LVS,DRC issues for 1 partition
• Involved in analysing and debugging non-equivalent points,aborts,not-mapped points in FEV
• Involved in analysis and debugging timing ERC using caliber tool and giving feedback to block owners.

Technology: Implemented in 10nm.

Tools: LEC Conformal, Calibre, Spyglass_LP, ICV, Primetime.

Design details: Design is having 3.84 Ghz as main clock frequency,6 partitions, 11 layers + RDL layers.

Challenges: Highly congested design ,fixing signal shorts are critical taking care of clock routes to avoid crosstalk issue.Implementation of timing ECO taking care of DRC,LVS.