MOULI YADLAPALLI

To be part of an organization, which uses my skills and its process of growth, challenges, and changes, while giving me ample opportunity to learn and enrich my competencies, to make meaningful and substantial contributions in management profiles of ASIC Physical Design in the VLSI industry.

Having 2 + years of Industrial experience in Physical design.

Career Break : | [March-2024 – JAN -2025 ] |
Took time off to recover from health issues and focus on well-being. Now fully recovered and ready to contribute effectively.

Projects Worked:

Project name : MTL

Client : Intel

Technology Node : 5nm

Block : Clock Frequency -1.4 GHz; Gate count – 4.1 M; Macro count - 71 macros; Metal Layers-16.

Tools Used : Synopsys ICC2, Primetime.

Project Description:`

• Took the responsibility to implement place and route for assigned block.
• Did manual placement of macros based on data flow lines, Macro family and ports.
• Did multiple floor plan and Placement experiments to reduce timing and congestion issues
• Placement of Macro cells with channel and, Placement blockages.
• Tried optimization techniques (like cell padding, path grouping,bounding) to resolve congestion and better timing.
• Implemented clock tree with targeted skew and latency.
• Implemented NDR rules to avoid crosstalk in clock nets.
• Analyzed and fixed Intra and Inter Timing and DRC are by several ECO Iterations.

Domain Specific Projects:

Project 1 : JBI Block.

Technology : 28nm.

Layers : 9 Metal layers.

Frequency : 500MHz

Supply Voltage : 1.16v

Block Statistics : 46 Macros, 38k+ Std Cells, Shape-Square.

IR drop budget : 58mv.

Role and Responsibilities:

• Working on Synthesis to improve better quality of netlist.
• Reading input files in synthesis stage to check if any missing constrained ports.
• Proficiently performed Automated PnR flow, showing strong analytical skills in analyzing input files from synthesis to routing stages.
• Led Floor planning efforts,achieving compact yet efficient designs with zero DRC errors and improved routability.
• Expertly managed Power planning,setting up critical parameters to meet calculated IR drop and ensure design integrity.
• Executed placement with a focus on power awareness and global congestion,leading to enhanced routability and reduced congestion.
• Analyzed Timing Reports at various stages,ensuring timing constraints such as skew,latency,and hold were met.
• Performed Routing stage and fixed issues such as opens,shorts,overlapping,cut-to-cut spacing.

Challenges:

• Timing Closure is a major Challenge.
• Macro placing as core area is very less.
• Fixing congestion in the huge hotspot area by applying blockages,keep out margin.
• After power planning congestion is more.
• Fixing of Setup and Hold time.

Project 2 : ORCATOP block.

Technology : 40nm.

Layers : 9 Metal layers.

Frequency : 833MHz

Supply Voltage : 1.1v

Block Statistics : 40 Macros, 52k Std Cells, Shape-Rectilinear.

IR drop budget : 55mv.

• Understanding the tool behavior by checking all the data fly lines where the max number of communications are there after that place the macros inside the core area.
• Building Power Plan to meet the IR Drop value, Adding Routing and Placement Blockages where needed to avoid DRC Errors, Missing vias, Floating wires and Design Checks.
• After Power Plan Analyzing Timing report, set false path to reduce high setup slack in placement stage, Post Placement Stage analyzing the timing report.
• Post Placement Stage analyzing the Global Route Congestion reducing them and again running the scripts many times.

I am confident of performing with a propensity towards excellence in a team as well as individually. I hereby declare that the above furnished details are true and correct to the best of my knowledge and belief.