Highly ambitious and optimistic individual with a quest to leverage my knowledge and skills. Complex problem-solver with analytical and driven mindset. Dedicated to achieving demanding development objectives according to tight schedules while producing impeccable code. Detail-oriented, organized and meticulous employee. Works at fast pace to meet tight deadlines. Enthusiastic team player ready to contribute to company success.
Router 1x3 – RTL design and Verification:
Architected the block level structure for the design
Implemented RTL using Verilog HDL. Architected the class based verification environment using SystemVerilog ➢ Verified the RTL model using SystemVerilog.