M S Sai Kamesh

Worked on PCIe gen 4:

1. Integrated PCIe RTL with VIP in SoC level and created Wrapper for PCIe (core, pcs, pma)

2. Configured PCIe VIP using Pureview and make sure all config of DUT should match with VIP monitor

3. Written test cases for PCIe (PCIe having interface with AXI master, AXI Slave and DBI for application Layer)

4. Implemented OutBound transaction sequences that uses AXI master interface and for slave interface

5. Written MSI Tlp sequence and done by programming of Config space registers with customized values.

6. Filed bugs on Inhouse PCS/Phy/clk blocks (core clock, AUX clk, pclk)

7. Implemented port driver for EP transactions

8. Implemented Bit bash sequences (With ral and Without ral)

9. written PME ACK and NAK sequences

10. Written TLP MEM sequences (Wr, Rd) by toggling and randomizing the header space information

11. LTSSM debugging and DLCMSM debugging for gen4 PCIe

RXDFE and Efuse :

1. Developed Complete IP level testbench for RXDFE and Efuse

2. Written sequences for register programming and injected test vectors for rxdfe and programming the coefficients of it.

3. Added checkers at each instance of pipeline and compared with actual test vectors in scoreboard

Clint : Intel (Worked on USB 3.2, PCH)

USB :

1. Experience on Debugging Intel Fabric (IOSF)

2. Experience in UVM methodology (written Test cases for USB 3.2, XHCI as Host), and debugged dew test cases

3. Debugging Experience on Constraint Random Verification at sub IP level (DBC, MFD, XHCI)

4. Debugged on Link Training status state machine , Link layer and protocol layer

5. Debugged on USB-DBC transactions and XHCI-USB transa ctions

6. Debugged on XHCI portsc registers and config registers

7. Includes the detailed verification of different categories of failure occurred in USB ip's Such as test components

8. Verified few testcases based on assertion verification, that depend on wake conditions (self wake and remote wake)

9. Debug Experience on RAL (Front door access) and on Config and status control registers.

10. Written testcases for Low power states of USB

CSME :

1. Verifying the data transactions from CSME to other IP's in SoC and configuring the CSME in secure mode

2. Found data transaction related issues when CSME was programmed in secure mode

3. Debug experience on CSME - IOSF protocol interconnect and coverage development

4. Implemented test cases for CSME low power modes

Worked in Specmen E project in verifying AHB-IOSF interconnect