Mugilan Mohan

Over 16 years of experience in Hardware development focusing on designing the board and package designs. Demonstrated experience in system architecture, high-speed interfaces, signal and power integrity, board bring up, debug and validation.

• Working as Silicon Packaging Architect for the SIPG group at Intel corporation, focused on Test chips designed in Intel advanced nodes like I3, I20A, I18A.
• Experienced in architecting package for Intel Test chips designed using external foundries like TSMC and Samsung.
• Experienced in designing packages using external IPs from suppliers like Synopsys, Cadence etc.
• Working directly with IP teams to gather requirements and capabilities of different IP blocks like DDR, PCIe, HSIO's, D2D (Die to Die) interconnect like UCIe's, on chip voltage regulators like FIVR, C2VR and foundational IPs like SRAM memories, GPIO & PLL's.
• Experienced in silicon floor planning and Die file design by working directly with SOC teams to meet the architectural requirements of package and platforms.
• Experienced in designing advance packages using D2D, 2.5D (EMIB) and 3D (Foveros) technologies.
• Experienced in mentor and lead the design engineers to drive the package design as per provided guidelines.
• 10+ years of experience in high-speed circuit digital design, PCB layout, EMI/EMC, signal Integrity and Power Integrity.
• Experienced in guiding PCB layout process like component placement, stack-up design, routing, signal length matching, power plane requirements and DFM/DFA for various high-speed boards.
• Experienced in designing low power and battery powered designs for IOT applications.
• Experienced in improving the performance of design, reducing the cost and time to market.
• Experienced in guiding PCB layout process like component placement, stack-up design, routing, signal length matching and power plane requirements for various high-speed boards.
• Experienced in AC and DC power integrity analysis like impedance plot, voltage drop, and current density.
• Experienced in pre- & post layout signal integrity analysis like eye diagram and frequency analysis.
• Co-ordinate with Firmware team for SOC's boot-up and hardware interfaces. And guide these two teams if they face any hardware related issues.
• Component selection for various hardware specific application and prepare Bill of Materials for component purchase.
• Experienced in board bring-up test like (power-up regulators and validate, check power-up sequence, and reset) and FPGA configuration check, JTAG chain validation and debug the circuits if there any fault on the hardware.
• Experienced in Rigid, Rigid-flex, High Speed & high-density PCB layouts using Cadence and Mentor tools.
• Experienced with designing to EMC/EMI/ESD and safety regulatory certifications.
• Experience in working with cross functional team in system development including firmware, mechanical and reliability engineering.
• Experience in facing customers to support their issues in the field and debug of customer boards to diagnose, trouble shoot and recommend workaround.
• Experience in FMEA, MTTF and Diagnostic Coverage calculations for Electronics products.
• Knowledge in functional safety standards for automotive and industrial applications like IEC61508, ISO26262, ISO25119 and ISO13849.
• Proven experience in handling multiple projects involving different stakeholders.
• Possess excellent analytical skills and leadership qualities.
• Excellent interpersonal communication skills

• Laboratory Equipment's: Oscilloscope, Function generator, TDR measurement, Spectrum Analyzer, LCR Meter and Network Analyzer.
• EMI/EMC Test instruments: ESD gun and EFT test set up
• Simulation tools: Pspice, LTspice, Cadence Sigrity, Ansys HFSS
• ECAD tools: Cadence, Altium, and Mentor Graphics designer

• Passport Number: N7682896
• Date of Birth: 03/22/83
• Nationality: Indian
• Marital Status: Married