NAGAVALLI S

Dynamic VLSI Design Intern at Excel VLSI Technologies with expertise in Verilog and SystemVerilog, adept at enhancing design efficiency through advanced simulation and verification techniques. Proven ability to collaborate effectively with senior engineers, optimizing low-power design strategies and ensuring robust circuit performance. Committed to delivering innovative solutions in digital design.

• NPTEL Courses
• Cadence Certifications, Orcad X Capture, Introduction to DFT, Virtuoso Pro, RTL to GDS
• Siemens Certification, Introduction to Tessent
• Infosys Springboard Certifications, Python Programming, Introduction to Deep Learning, VLSI Global Routing Optimization Using Deep Learning Algorithm

Optimization of VLSI Global Routing using Deep learning Algorithm.Executed projects on ALU, Vending Machine, Synchronous Clock Divider, Shift Registers, and AMBA protocols. Hardware Modelling using Verilog, Designed and implemented I2C communication protocol in Verilog. Implementation of UART using SystemVerilog, designed a UART module for serial communication AMBA Protocols (APB, AHB, AXI), Designed Verilog-based modules for AMBA protocol compliance. Design and Implementation of ALU & Synchronous Clock Divider, Developed Verilog-based ALU for arithmetic and logic operations. Nuclear Power Plant Monitoring System using IoT, Integrated sensor networks for real-time monitoring and predictive maintenance. Fingerprint Door Lock System Using Arduino, Developed a biometric-based security system using fingerprint sensors and Arduino.

Journal Name: International Journal of Engineering and Science Invention (IJESI)

Publication Date: Oct 2024

Authored a paper titled 'VLSI Global Routing Using Deep Learning Algorithm,' proposed a novel deep learning-based approach to predict congestion during the global routing phase of VLSI design, enabling more efficient optimization, and reducing routing congestion compared to traditional methods

Journal Name: International Journal of Scientific Research and Engineering Trends (IJSRET)

Publication Date: May-June 2023

Authored a paper, 'AI in VLSI Routing: A Review,' exploring applications and advancements in using artificial intelligence for very large-scale integration (VLSI) routing. Published in IJSRET, the review highlights my research capabilities and in-depth understanding of AI's role in enhancing routing efficiency, reducing power consumption, and optimizing overall performance in chip design. It contributes valuable insights to the intersection of artificial intelligence and VLSI design.