Summary
Overview
Work History
Education
Skills
Websites
Certification
Projects
Professional Training Experience
Timeline
Generic

NANDHA KISHORE DINDU

Bangalore

Summary

Seeking an entry-level position in VLSI domain to begin my career in a high-level professional environment where I can contribute to the growth of the organization while constantly enhancing my skills and abilities.

Overview

1
1
year of professional experience
1
1
Certification

Work History

Professional Training

VLSI GURU INSTITUTE
Bangalore
05.2024 - 03.2025

Education

B Tech - Electronics And Communication Engineering

Jawaharlal Nehru Technological University
Ananthapur
05.2024

Skills

Technical subjects

  • Verilog
  • System Verilog
  • Digital Electronics
  • UVM

Protocols

  • APB
  • AXI
  • SPI
  • Ethernet

Tools

  • Modelsim
  • Vivado
  • Questa Sim
  • EDA Playground

Scripting Language

  • Python

Certification

  • Arm India VLSI to system design: Silicon to end application approach - participation, 09/23
  • Internet Of Things (IOT) course - Microsoft
  • Data Analytics and python full stack course completed - Codegnan.
  • National Programming on Technology Enhanced Learning (NPTL)

Projects

Verification of IP development for the AMBA AXI4.0 protocol using UVM

AXI3.0 is an AMBA protocol used for high-performance applications, and AXI3.0 supports various features, like out-of-order transactions

  • Develop VIP Architecture to be compatible with both master and slave behaviour.
  • List the AXI features, and develop a test plan for validating the AHB VIP
  • Develop AXI VIP components.
  • Integrated AXI master VIP with slave VIP

Ethernet MAC functional verification using SV and UVM

Ethernet MAC is a MAC core with transmit and receive logic working at 100 Mbps. The design consists of five sub-modules, including the DMA controller. 

  • Ethernet MAC core: A core that handles the MAC layer functions, including frame processing, address resolution, and collision handling.
  • Ethernet PHY (Physical Layer): The PHY layer handles the physical transmission of data over the network medium.
  • Ethernet Transceiver: A device that converts electrical signals to optical signals and vice versa for Ethernet communication over optical fibers

Design and Verification of SPI Controller

  • The SPI controller is a design block that acts as an interface between the processor and SPI slaves, and the SPI architecture is based on one master and multiple slaves.
  • SPI controller has two interfaces: one is the APB interface used for configuring the SPI registers, address, and data, and the other is
  • SPI interface used for connecting with SPI slaves. SPI uses SCLK, MOSI, and XS to connect the master to the slave

Professional Training Experience

VLSI GURU INSTITUTE, Bangalore, Karnataka, 05/24, 03/25

Timeline

Professional Training

VLSI GURU INSTITUTE
05.2024 - 03.2025

B Tech - Electronics And Communication Engineering

Jawaharlal Nehru Technological University
NANDHA KISHORE DINDU