NARESH KUMAR GARRAPALLI
Software Engineer
Warangal,Telangana
Summary
Practical Associate Consultant with expertise in managing priorities to meet deadlines and realize high-quality outcomes. Committed to establishing credibility and developing relationships with associates and managers. Strong conceptual thinking skills and new concepts acquisition.
Overview
5
5
years of professional experience
4
4
Years of B.Tech
Work History
Associate Consultant
Capgemini Technologies and Services
Hyderabad
10.2022 - Current
- SLT (, Landscape Transform) tracks and read the data and pushes to cloud storage bucket
- CDF (cloud data fusion) pulls the data from cloud storage bucket and writes it to
- Bigquery
- Bigquery Raw data -> Cloud composer -> Bigquery CDC data
- Finally, by using CDC data we need to do analytics by using Looker tool
- Worked on Cloud SQL Database service in GCP
- Cloud Pub/Sub is used for ingesting the data from different sources like sensor data from IoT devices, log files from application
- Google Cloud Storage is used for storing the unstructured data and object data
- Worked on Compute engine VM instances
- Worked on SQL Queries like DDL, DML, DCL and TCL commands
- Knowledge on Apache Spark using python.
Senior Analyst/Software Engineer
Capgemini Technologies and Services
Hyderabad
07.2021 - 10.2022
ASIC Physical Design Engineer
Semicon Techno Labs
Bangalore
08.2018 - 02.2019
- Expertise to Understand a VLSI – ASIC Flow and VLSI – FPGA Flow.
- Good Understanding of ASIC – Physical Design flow Net list to GDSII i.e., Design Import, SanityChecks, Floor-plan, Placement, CTS and Routing.
- Good Understanding of the inputs and outputs of all the stages in the Physical Design.
- Efficient in High Count Macro Placement During Floor-planning.
- Placing Std Cells in core Area and Checking Congestion, Timing Analysis (Setup) and TimingConstraints (Max. Transition, Max. Capacitance and Max. Fan-out).
- Delivering The Real Clock Which Requires Clock Signal to All Flip-Flop Present in CTS Stage andmain goal for CTS is Min. Skew and Latency.
- Finally, Routing The Signal Nets.
- Firstly we have to check Crosstalk and Timing DRC’s (Max. Transition, Max. Capacitance andMax. Fan-out) because it may effect to Setup and Hold Timing in CTS and Routing Stages.
- We have to Balanced the Skew and Latency at CTS Stage. +Ve Skew may Effect When Capture Datacomes late than Launch flop we get Setup Violation and vice-versa for –ve Skew.
- The Main Difference between ASIC and FPGA Flow is After Fabrication Process is completedwecan’t write RTL Code and Synthesized it again But We Can Do it in FPGA Flow
- I have Worked on Different Technologies like 14nm,28nm and 45nm.
- I Observed that in 45nm, 28nm and 14nm technologies such that technology decreases Std.cells Increases, Metal layers will increase so, it be more complexity to design by maintain timing, power andarea.
- If width of the Metal decreases and Std.cells Width decreases it may effect to delay and also a IRdropissues because more resistances.
Education
B.Tech - Electronics And Communications Engineering
Vaagdevi College of Engineering
Warangal, Telangana, India 06.2014 - 05.2018
Intermediate -
SR Junior College
Warangal 06.2012 - 04.2014
SR National High School
Warangal 06.2011 - 03.2012
Skills
GCP Data Engineer
undefinedAccomplishments
- Used Microsoft Excel to develop inventory tracking spreadsheets.
- Achieved Result through effectively helping with Task.
- Certification of Google cloud Professional Data Engineer.
Timeline
Associate Consultant
Capgemini Technologies and Services
10.2022 - Current
Senior Analyst/Software Engineer
Capgemini Technologies and Services
07.2021 - 10.2022
ASIC Physical Design Engineer
Semicon Techno Labs
08.2018 - 02.2019
B.Tech - Electronics And Communications Engineering
Vaagdevi College of Engineering
06.2014 - 05.2018
Intermediate -
SR Junior College
06.2012 - 04.2014
SR National High School
06.2011 - 03.2012
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