Summary
Work History
Education
Skills
Professional Summary
Projects
Additional Information
Timeline
Generic

Naveen Nagarapu

Hardware Design Engineer

Summary

To work in a challenging and dynamic environment and to keep adding value to the organization that I represent and serve, while also concurrently upgrading my skills and knowledge.

Work History

Hardware Design Engineer

Intel Corporation
Bangalore
07.2022 - Current

Role:

  • Schematic entry, design execution, PDG intercept, feasibility analysis
  • BOM optimization and control
  • Layout Review
  • Design Documentation
  • Correlating design decisions with Lab measurements

Internship

Intel Corporation, EMC
Bangalore
06.2021 - 07.2022

Role:

  • Responsible for ensuring electrical/ electronic system integration and compliance will all applicable Electromagnetic Compatibility (EMC) standards and requirements
  • Route cause analysis of EMI issues in DC/DC Voltage Regulator and developing mitigation techniques.
  • Developing novel EMI shielding solutions for Power Converters and Devices and improvising the existing Stripline test setup for EMI shielding
  • Design and simulation of 3D model of test setups and antennas in HFSS and CST microwave studio

Sr Executive

TATA POWER DELHI DISTRIBUTION LIMITED
New Delhi
07.2017 - 12.2018

Role:

  • Operation and maintenance engineer responsible for uninterruptible power supply
  • Fault handling, improvement in pre laid network
  • Responsible for planning of predictive and preventive maintenance through data analysis and site surveys. This involve Transformers, ACBs, DD and Feeders etc..
  • In depth data acquiring and analysis for monitoring of AT&C, SAIDI, SAIFI and theft identification.

Education

M.Tech - Power Electronics and Drives

National Institute of Technology, Warangal
08.2020 - 06.2022

B.Tech - Electrical Engineering

Motilal Nehru National Institute of Technology
07.2013 - 05.2017

Intermediate - PCM

NRI Junior College
08.2011 - 04.2013

S.S.C -

SPR Schools
07.2010 - 03.2011

Skills

Allegro Entry HDL conceptundefined

Professional Summary

Motivated engineer familiar with design electronic products both at signal and power levels

  • Strong background in power electronics design with DC and AC systems.
  • Hands-on experience in analyzing/designing/validating power electronics circuit and system.
  • Good understanding in the analysis, modelling, design and implementation of controller for power electronics converters like DC-DC converter.
  • Experience in Type C design, USB Power delivery designs
  • Experience in developing and implementing various analog control techniques likes voltage mode control, current mode control, constant on time control, peak/valley current control etc for DC-DC converters.
  • Good knowledge in component selection like Inductor, Capacitor, diode, MOSFET for power electronics converters based on worse case calculation.
  • Good understanding of EMC ,EMI concepts and Maxwells equations.
  • Worked on EMI mitigation issues on DC/DC voltage regulators.
  • Developed a novel method for EMI Gasket characterization.
  • Experience in Mixed signal multi-layer board layout techniques considering signal and power integrity constraints.
  • Experience in circuit and system simulation tool like MATLAB/SIMULINK, LTspice, etc.
  • Experience in Schematic design in Concept HDL, Hands on with allegro layout tool.
  • Experience in PnP and HMB analysis of DRAM and DRAMless SSDs.
  • Strong command in preparing design documents-Power sequence diagram, block diagram of experimental set-up, harness diagram, experimental test template.
  • Proficient in technical writing.
  • Excellent communication and Interpersonal skills.

Projects

  

Project Title:   TCSS AICs for Panther Lake silicon validation card

Brief Description: 8 different Type-C Subsystem Add In Cards to validate all the possible silicon supported configurations like DP, HDMI, TBT, eDP, retimer/less. Responsible for schematic design, BOM management, design documentation, connectivity check


Project Title:  Performance analysis of DRAM and DRAM less SSDs with 2230 and 2280 form factor and HMB performance 

Brief Description: As day by day need for small form factor chips is increasing. In a way to design, small form factor storage device like SSDs is dropping DRAM chip. The background of this analysis is to narrow down the design choice of DRAM and DRAM less SSDs.


Project Title:  Deliver quality T3 stack based Derivative core design for Intel Meteor lake(MTL) P segment AEP

Brief Description: .


Project Title:  A novel approach for EMI shielding gasket characterization 

Brief Description: Radio frequency noise is generated by platform components such as SOC, DDR, SSD, etc. can degrade signal to noise ratio of systems RF receiver which in turn degrades the performance of wireless connectivity. In order reduce the effect of the noise, gaskets are employed between metal to metal contacts. So a new approach is developed to characterize the EMI gasket in an efficient and effective way.


Project Title:  Mitigation of EMI issues in electronic converters and devices

Brief Description: The leakage of EMI issues is taking place even after shielding enclosure are used, EMI caused by one device is affecting the surrounding devices. This project is to find the major route cause of EMI issue in electronic devices and to find solutions for mitigation of the issue. 


Project Title:  Design of high rated power converter (Both simulation and hardware) for balancing power in individual phase in feeders.

Brief Description: In practical power distribution, there is unbalance in feeder lines due to random connection of load of two different phases. To balance the power in each phase, a power converter is designed such that it balances the power between the individual phases.


Project Title:  A hybrid charger of conductive and inductive modes of Electric Vehicles

Brief Description: This proposes a hybrid charger system where the high frequency transformer becomes of an on-board DC-DC converter becomes the coupling point between the conductive and inductive charging. Using this coupling point, the circuit utilizes same components for both conductive and inductive modes.

Additional Information

  • Date of Birth : 26/01/1996
  • Nationality : Indian
  • Language known : English, Hindi, Telugu
  • Permanent Address : 1-1-16/8/5, Hydernagar, Hyderabad, Telangana, 500072


I hereby declare that the details and information given above are complete and true to the best of my knowledge .


Signature: Naveen Nagarapu

Date: 26/06/2023

Timeline

Hardware Design Engineer

Intel Corporation
07.2022 - Current

Internship

Intel Corporation, EMC
06.2021 - 07.2022

M.Tech - Power Electronics and Drives

National Institute of Technology, Warangal
08.2020 - 06.2022

Sr Executive

TATA POWER DELHI DISTRIBUTION LIMITED
07.2017 - 12.2018

B.Tech - Electrical Engineering

Motilal Nehru National Institute of Technology
07.2013 - 05.2017

Intermediate - PCM

NRI Junior College
08.2011 - 04.2013

S.S.C -

SPR Schools
07.2010 - 03.2011
Naveen NagarapuHardware Design Engineer